Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12332737 | Method and apparatus for fault indication propagation and fault masking in a hierarchical arrangement of systems | Shruti Singla, Rohan Poudel, Shreya Singh, Sandeep Kumar Arya, Bipin Gupta | 2025-06-17 |
| 12242335 | Method and apparatus for fault aggregation and support for virtualization | Aarul Jain, Ashu Gupta | 2025-03-04 |
| 12105583 | Fault recovery system for functional circuits | Neha Srivastava, Andres Barrilado Gonzalez | 2024-10-01 |
| 12050512 | Dynamic configuration of reaction policies in virtualized fault management system | Shreya Singh, Sandeep Kumar Arya | 2024-07-30 |
| 11513153 | System and method for facilitating built-in self-test of system-on-chips | Rohan Poudel, Anurag Jindal, Joseph Wright, Nipun Mahajan, Shruti Singla | 2022-11-29 |
| 11334409 | Method and system for fault collection and reaction in system-on-chip | Jehoda Refaeli, Ankush Sethi, Shreya Singh | 2022-05-17 |
| 10831578 | Fault detection circuit with progress register and status register | Jan Chochola, Ashish Gupta, David Baca | 2020-11-10 |
| 10261924 | Communication system for transmitting and receiving control frames | Rajan Kapoor, Arvind Kaushik, Puneet Khandelwal | 2019-04-16 |
| 9355691 | Memory controller | Prabhjot Singh, Amit Rao | 2016-05-31 |
| 8990549 | Method and system for booting electronic device from NAND flash memory | Nitin Gera, Amit Rao, Prabhjot Singh | 2015-03-24 |
| 8321649 | Memory controller address and data pin multiplexing | Dhruv Satsangi | 2012-11-27 |
| 8285908 | Bus bridge and method for interfacing out-of-order bus and multiple ordered buses | Amar Nath Deogharia | 2012-10-09 |