Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12265776 | Identifying test coverage gaps for integrated circuit designs based on node testability and physical design data | Kapil Narula, Rahul Kalyan, Hongkun Liang | 2025-04-01 |
| 12237217 | Methods of exposing conductive Vias of semiconductor devices and related semiconductor devices | Hongqi Li, Irina Vasilyeva | 2025-02-25 |
| 11821946 | Built in self test (BIST) for clock generation circuitry | Jorge Arturo Corso Sarmiento | 2023-11-21 |
| 11742282 | Conductive interconnects | Jordan D. Greenlee, Rita J. Klein, Everett A. McTeer, John D. Hopkins, Shuangqiang Luo +3 more | 2023-08-29 |
| 11513153 | System and method for facilitating built-in self-test of system-on-chips | Rohan Poudel, Joseph Wright, Nipun Mahajan, Shruti Singla, Hemant Nautiyal | 2022-11-29 |
| 11144677 | Method and apparatus for digital only secure test mode entry | Stefan Doll, Thomas Henry Luedeke, Nikila Krishnamoorthy, Hubert Glenn Carson, Jr., Hilario Manuel Garza +3 more | 2021-10-12 |
| 11011420 | Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods | Hongqi Li, Jin Lu, Shyam Ramalingam | 2021-05-18 |
| 10847442 | Interconnect assemblies with through-silicon vias and stress-relief features | Hongqi Li, Jin Lu, Gowrisankar Damarla, Shyam Ramalingam | 2020-11-24 |
| 10546777 | Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods | Hongqi Li, Jin Lu, Shyam Ramalingam | 2020-01-28 |
| 10475810 | Conductive components and memory assemblies | Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, David Ross Economy, John Mark Meldrim | 2019-11-12 |
| 10014319 | Conductive components and memory assemblies | Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, David Ross Economy, John Mark Meldrim | 2018-07-03 |
| 9922875 | Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods | Hongqi Li, Jin Lu, Shyam Ramalingam | 2018-03-20 |
| 9773807 | Conductive components and memory assemblies | Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, David Ross Economy, John Mark Meldrim | 2017-09-26 |
| 9766289 | LBIST debug controller | Mayank Parasrampuria, Sagar Kataria | 2017-09-19 |
| 9754825 | Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods | Hongqi Li, Jin Lu, Shyam Ramalingam | 2017-09-05 |
| 9627295 | Devices, systems and methods for manufacturing through-substrate vias and front-side structures | Jian He, Lalapet Rangan Vasudevan, Kyle K. Kirby, Hongqi Li | 2017-04-18 |
| 9599673 | Structural testing of integrated circuits | Nipun Mahajan | 2017-03-21 |
| 9599672 | Integrated circuit with scan chain having dual-edge triggered scannable flip flops and method of operating thereof | Kumar Abhishek, Nishant Madan, Mayank Tutwani | 2017-03-21 |
| 9568551 | Scan wrapper circuit for integrated circuit | Sagar Kataria, Abhishek Mahajan, Mayank Parasrampuria | 2017-02-14 |
| 9330975 | Integrated circuit substrates comprising through-substrate vias and methods of forming through-substrate vias | Hongqi Li | 2016-05-03 |
| 9305865 | Devices, systems and methods for manufacturing through-substrate vias and front-side structures | Jian He, Lalapet Rangan Vasudevan, Kyle K. Kirby, Hongqi Li | 2016-04-05 |
| 9298572 | Built-in self test (BIST) with clock control | Nisar Ahmed, Nipun Mahajan | 2016-03-29 |
| 9297855 | Integrated circuit with increased fault coverage | Huangsheng Ding, Ling Wang | 2016-03-29 |
| 9285424 | Method and system for logic built-in self-test | Nitin Singh, Amit Jindal | 2016-03-15 |
| 9213063 | Reset generation circuit for scan mode exit | — | 2015-12-15 |