Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367127 | Dynamic response generation based on an anomaly associated with a software application | Pravin Kumar Sankari Bhagavathiappan, Amit Mishra, Yogesh Raghuvanshi | 2025-07-22 |
| 12301761 | Intelligent routing signaling system | Amit Mishra, Yogesh Raghuvanshi, S. B. Pravin Kumar, Balaji Sugumar, Yaksh Kumar Singh | 2025-05-13 |
| 12153908 | Source code conversion from an original computer programming language to a target programming language | Amit Mishra, Yaksh Kumar Singh, Yogesh Raghuvanshi, Pravin Kumar Sankari Bhagavathiappan | 2024-11-26 |
| 12124828 | Source code validation based on converting the source code to a non-programming language | Amit Mishra, Yaksh Kumar Singh, Yogesh Raghuvanshi, Pravin Kumar Sankari Bhagavathiappan | 2024-10-22 |
| 11513153 | System and method for facilitating built-in self-test of system-on-chips | Rohan Poudel, Anurag Jindal, Joseph Wright, Shruti Singla, Hemant Nautiyal | 2022-11-29 |
| 11461205 | Error management system for system-on-chip | Neha Bagri, Abhinav Gaur | 2022-10-04 |
| 10810273 | Auto identification and mapping of functional attributes from visual representation | Pinak Chakraborty, Gaurav Bansal, Yogesh Raghuvanshi | 2020-10-20 |
| 9599673 | Structural testing of integrated circuits | Anurag Jindal | 2017-03-21 |
| 9298572 | Built-in self test (BIST) with clock control | Nisar Ahmed, Anurag Jindal | 2016-03-29 |
| 8793641 | System and method for determining power leakage of electronic circuit design | Amit Roy, Shyam S. Gupta, Vijay Tayal, Chetan Verma | 2014-07-29 |
| 8458541 | System and method for debugging scan chains | Sandeep Jain, Nikila Krishnamoorthy, Abhishek Chaudhary, Saurabh Chauhan | 2013-06-04 |