Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9292651 | System for partitioning integrated circuit design based on timing slack | Chetan Verma, Amit Kumar Dey, Ashis Maitra, Kulbhushan Misri, Amit Roy +1 more | 2016-03-22 |
| 9176522 | Dual-edge gated clock signal generator | Amit Kumar Dey, Himanshu Mangal, Kulbhushan Misri, Amit Roy, Chetan Verma | 2015-11-03 |
| 9166585 | Low power inverter circuit | Amit Roy, Zhihong Cheng, Amit Kumar Dey, Chetan Verma | 2015-10-20 |
| 9003351 | System and method for reducing power consumption of integrated circuit | Chetan Verma, Kushagra Khorwal, Amit Roy, Rounak Roy | 2015-04-07 |
| 8887120 | Timing path slack monitoring system | Chetan Verma, Amit Kumar Dey, Amit Roy | 2014-11-11 |
| 8803591 | MOS transistor with forward bulk-biasing circuit | Amit Roy, Amit Kumar Dey, Kulbhushan Misri, Chetan Verma | 2014-08-12 |
| 8793641 | System and method for determining power leakage of electronic circuit design | Amit Roy, Shyam S. Gupta, Nipun Mahajan, Chetan Verma | 2014-07-29 |
| 8762922 | System for reducing leakage power of electronic circuit | Amit Roy, Chetan Verma | 2014-06-24 |
| 8527935 | System for reducing power consumption of electronic circuit | Chetan Verma, Amit Roy | 2013-09-03 |