Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12259764 | Architecture for managing asynchronous resets in a system-on-a-chip | Kumar Abhishek, Yi Zheng, Nishant Kumar | 2025-03-25 |
| 12124347 | System and method for managing secure memories in integrated circuits | Gautam Tikoo, Harshit Saxena | 2024-10-22 |
| 12105583 | Fault recovery system for functional circuits | Hemant Nautiyal, Andres Barrilado Gonzalez | 2024-10-01 |
| 11797373 | System and method for managing faults in integrated circuits | Ankur Behl | 2023-10-24 |
| 11609821 | Method and system for managing fault recovery in system-on-chips | Ankur Behl | 2023-03-21 |
| 11550684 | Testing of lockstep architecture in system-on-chips | Krishan Bansal | 2023-01-10 |
| 11520653 | System and method for controlling faults in system-on-chip | Ankur Behl, Garima Sharda | 2022-12-06 |
| 11482992 | Clock sweeping system | Ateet Mishra, Ankur Behl, Nancy Mishra, Kriti Garg | 2022-10-25 |
| 11422185 | System and method for testing critical components on system-on-chip | Garima Sharda | 2022-08-23 |
| 11175340 | System and method for managing testing and availability of critical components on system-on-chip | Shreya Singh | 2021-11-16 |
| 11018657 | Clock glitch alerting circuit | Rohit Kumar Sinha, Stefan Doll | 2021-05-25 |
| 9891654 | Secure clock switch circuit | Rohit Kumar Sinha, Vandana Sapra, Mandeep Singh, Sidharth S. Singh | 2018-02-13 |
| 7808279 | Low power, self-gated, pulse triggered clock gating cell | Anubhav Srivastava, Abhishek Mahajan | 2010-10-05 |