Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5835946 | High performance implementation of the load reserve instruction in a superscalar microprocessor that supports multi-level cache organizations | Michael S. Allen, Robert Alan Cargnoni, Jose M. Nunez, David W. Todd, Jen-Tian Yen | 1998-11-10 |
| 5682495 | Fully associative address translation buffer having separate segment and page invalidation | Lew G. Chua-Eoan, Pei-Chun Liu, Chih-Jui Peng | 1997-10-28 |
| 5604879 | Single array address translator with segment and page invalidate ability and method of operation | Chua-Eoan Lew, Pei-Chun Liu, Chih-Jui Peng | 1997-02-18 |
| 5530822 | Address translator and method of operation | Lew G. Chua-Eoan, Chih-Jui Peng | 1996-06-25 |