Issued Patents All Time
Showing 25 most recent of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12373215 | Using a next fetch predictor circuit with short branches and return fetch groups | Niket K. Choudhary, Mary D. Brown, Ethan Schuchman, Ian D. Kountanis, Douglas C. Holman +3 more | 2025-07-29 |
| 12265823 | Trace cache with filter for internal control transfer inclusion | Ilhyun Kim, Niket K. Choudhary, Muawya M. Al-Otoom, Pruthivi Vuyyuru | 2025-04-01 |
| 11893413 | Virtual channel support using write table | Michael D. Snyder, Deepak Limaye, Brett S. Feero, Rohit Gupta | 2024-02-06 |
| 11880308 | Prediction confirmation for cache subsystem | Mary D. Brown, Balaji Kadambi, Mahesh K. Reddy | 2024-01-23 |
| 11487667 | Prediction confirmation for cache subsystem | Mary D. Brown, Balaji Kadambi, Mahesh K. Reddy | 2022-11-01 |
| 11080188 | Method to ensure forward progress of a processor in the presence of persistent external cache/TLB maintenance requests | Jonathan Y. Tong, Christopher L. Colletti, David E. Kroesche, James Nolan Hardage | 2021-08-03 |
| 10901484 | Fetch predition circuit for reducing power consumption in a processor | Conrado Blasco, Ramesh Gunna, Ian D. Kountanis, Shyam Sundar, André Seznec | 2021-01-26 |
| 10552323 | Cache flush method and apparatus | Todd A. Venton, Jonathan Y. Tong, David E. Kroesche | 2020-02-04 |
| 10402326 | Accessing memories in coherent and non-coherent domains in a computing system | Mahesh K. Reddy, David Williamson | 2019-09-03 |
| 10241557 | Reducing power consumption in a processor | Conrado Blasco, Ramesh Gunna, Ian D. Kountanis, Shyam Sundar, André Seznec | 2019-03-26 |
| 9940262 | Immediate branch recode that handles aliasing | Shyam Sundar, Richard F. Russo, Conrado Blasco | 2018-04-10 |
| 9772851 | Retrieving instructions of a single branch, backwards short loop from a local loop buffer or virtual loop buffer | Michael L. Karm, Brian R. Mestan, David Mui | 2017-09-26 |
| 9632788 | Buffering instructions of a single branch, backwards short loop within a virtual loop buffer | Michael L. Karm, Brian R. Mestan, David Mui | 2017-04-25 |
| 9632791 | Cache for patterns of instructions with multiple forward control transfers | Muawya M. Al-Otoom, Ian D. Kountanis, Michael L. Karm | 2017-04-25 |
| 9524011 | Instruction loop buffer with tiered power savings | Michael L. Karm, Ian D. Kountanis, David Williamson | 2016-12-20 |
| 9395992 | Instruction swap for patching problematic instructions in a microprocessor | Richard W. Doing, Kevin N. Magill, James O. Tingen, Todd A. Venton | 2016-07-19 |
| 9395995 | Retrieving instructions of a single branch, backwards short loop from a virtual loop buffer | Michael L. Karm, Brian R. Mestan, David Mui | 2016-07-19 |
| 9311098 | Mechanism for reducing cache power consumption using cache way prediction | Conrado Blasco-Allue | 2016-04-12 |
| 9052910 | Efficiency of short loop instruction fetch | Michael L. Karm, Brian R. Mestan, David Mui | 2015-06-09 |
| 9037837 | Hardware assist thread for increasing code parallelism | Hung Q. Le, Raul E. Silvera, Balaram Sinharoy | 2015-05-19 |
| 8898441 | Obtaining and releasing hardware threads without hypervisor involvement | Giles R. Frazier | 2014-11-25 |
| 8793474 | Obtaining and releasing hardware threads without hypervisor involvement | Giles R. Frazier | 2014-07-29 |
| 8719554 | Scaleable status tracking of multiple assist hardware threads | Richard Louis Arndt, Giles R. Frazier | 2014-05-06 |
| 8713290 | Scaleable status tracking of multiple assist hardware threads | Richard Louis Arndt, Giles R. Frazier | 2014-04-29 |
| 8612730 | Hardware assist thread for dynamic performance profiling | Venkat R. Indukuru, Alexander Erik Mericas, Balaram Sinharoy, Zhong Liang Wang | 2013-12-17 |