Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12242855 | Coprocessor operation bundling | Aditya Kesiraju, Nikhil Gupta, Viney Gautam | 2025-03-04 |
| 12001847 | Processor implementing parallel in-order execution during load misses | Justin M. Deinlein, Michael L. Karm, David E. Kroesche | 2024-06-04 |
| 11893413 | Virtual channel support using write table | Michael D. Snyder, Ronald P. Hall, Deepak Limaye, Rohit Gupta | 2024-02-06 |
| 11886340 | Real-time processing in computer systems | Jonathan Y. Tong, David E. Kroesche | 2024-01-30 |
| 11755328 | Coprocessor operation bundling | Aditya Kesiraju, Nikhil Gupta, Viney Gautam | 2023-09-12 |
| 11556485 | Processor with reduced interrupt latency | Jonathan Y. Tong, Christopher L. Colletti, David E. Kroesche, Gagan Anand, Matthew Stone +1 more | 2023-01-17 |
| 11210100 | Coprocessor operation bundling | Aditya Kesiraju, Nikhil Gupta, Viney Gautam | 2021-12-28 |
| 11093249 | Methods for partially preserving a branch predictor state | Conrado Blasco, David Williamson, Ian D. Kountanis, Shih-Chieh Wen | 2021-08-17 |
| 11055102 | Coprocessor memory ordering table | Aditya Kesiraju, Nikhil Gupta | 2021-07-06 |
| 10922232 | Using cache memory as RAM with external access support | David E. Kroesche, David Williamson | 2021-02-16 |
| 10776125 | Coprocessor memory ordering table | Aditya Kesiraju, Nikhil Gupta | 2020-09-15 |
| 10613867 | Suppressing pipeline redirection indications | Sendil Srinivasan | 2020-04-07 |
| 10445091 | Ordering instructions in a processing core instruction buffer | — | 2019-10-15 |
| 10223123 | Methods for partially saving a branch predictor state | Conrado Blasco, David Williamson, Ian D. Kountanis, Shih-Chieh Wen | 2019-03-05 |
| 10203959 | Subroutine power optimiztion | — | 2019-02-12 |
| 10007616 | Methods for core recovery after a cold start | David Williamson, Jonathan J. Tyler, Mary D. Brown | 2018-06-26 |
| 9880961 | Asynchronous bridge circuitry and a method of transferring data using asynchronous bridge circuitry | Klas Magnus Bruce | 2018-01-30 |
| 9477600 | Apparatus and method for shared cache control including cache lines selectively operable in inclusive or non-inclusive mode | Jamshed Jalal, Mark David Werkheiser, Michael Filippo | 2016-10-25 |
| 9411362 | Storage circuitry and method for propagating data values across a clock boundary | Michael Filippo | 2016-08-09 |
| 8935485 | Snoop filter and non-inclusive shared cache memory | Jamshed Jalal, Mark David Werkheiser, Michael Filippo | 2015-01-13 |
| 8775754 | Memory controller and method of selecting a transaction using a plurality of ordered lists | Michael Andrew Campbell, Christopher Wrigley | 2014-07-08 |
| 8490107 | Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels | Jamshed Jalal, Mark David Werkheiser, Michael Filippo, Ramamoorthy Guru Prasadh, Phanindra Kumar Mannava | 2013-07-16 |
| 8301932 | Synchronising between clock domains | Timothy Nicholas Hay | 2012-10-30 |
| 8285912 | Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure | Peter Andrew Riocreux, Andrew David Tune | 2012-10-09 |