Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
AT

Andrew David Tune — 55 Patents

NVIDIA: 55 patents #58 of 7,811Top 1%
Dronfield, GB: #1 of 17 inventorsTop 6%
Overall (All Time): #45,454 of 4,157,543Top 2%
55 Patents All Time
Andrew David Tune has been granted 55 US patents while listed as an inventor at NVIDIA. The first was granted in 2006 and the most recent in November 2025. Andrew David Tune ranks #45,454 of 4,157,543 US inventors in our database (top 1.1%). Patent records list Andrew David Tune in Dronfield, GB.

Patents per Year

Patents granted per year, 2006 to 2025Bar chart with a peak of 8 patents in 2016.peak 82006: 1 patents20062010: 2 patents2011: 1 patents20112012: 5 patents2013: 1 patents20132014: 2 patents2015: 3 patents20152016: 8 patents2017: 4 patents20172018: 4 patents2019: 5 patents20192020: 5 patents2021: 3 patents20212022: 3 patents2024: 4 patents20242025: 4 patents2025

Issued Patents All Time

Showing 1–25 of 55 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12481593 Method and apparatus for reduction of recurring cache misses Lorenzo Di Gregorio 2025-11-25
12423236 Coherency control 2025-09-23
12422992 Increased throughput for writes to memory Akshay Kumar, Rahul Mathur, Edward M. McCombs, Sean James Salisbury, Gaurav Kumar 2025-09-23
12399735 Managing transaction request identifiers and indicators to control or bypass in-order handling of transaction requests Daniel Sara, Guanghui Geng 2025-08-26
12181967 Patrol scrubbing cycle for data storage circuitry Cyrille Dray 2024-12-31 $53,026,000
12174738 Circuitry and method Sean James Salisbury, Edward M. McCombs 2024-12-24 $46,652,000
12087353 Burst read with flexible burst length for on-chip memory Edward M. McCombs, Sean James Salisbury, Rahul Mathur, Hsin-Yu Chen, Phani Raja Bhushan Chalasani 2024-09-10 $55,532,000
12056058 Cache replacement control Andrew Brookfield Swaine 2024-08-06 $58,896,000
11314676 Apparatus and method for buffered interconnect Sean James Salisbury 2022-04-26
11314675 Interface circuitry for exchanging information with master, home, and slave nodes using different data transfer protocols Guanghui Geng, Daniel Sara, Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal 2022-04-26
11288195 Data processing 2022-03-29
10956205 Data processing Alistair Crone Bruce 2021-03-23
10938622 Interconnection network for integrated circuit with fault detection circuitry provided locally to an upstream location Julian Jose Hilgemberg Pontes, Sean James Salisbury 2021-03-02
10929060 Data access request specifying enable vector 2021-02-23
10771194 Interconnection network for integrated circuit Guanghui Geng, Zheng Xu 2020-09-08
10761561 Error checking for primary signal transmitted between first and second clock domains Saira Samar Malik, David Joseph Hawkins, Guanghui Geng, Julian Jose Hilgemberg Pontes 2020-09-01
10740269 Arbitration circuitry 2020-08-11
10592439 Arbitrating circuitry and method Peter Andrew Riocreux, Alessandro Grande 2020-03-17
10579469 Interconnection network for integrated circuit Guanghui Geng 2020-03-03
10489323 Data processing system for a home node to authorize a master to bypass the home node to directly send data to a slave Guanghui Geng, Daniel Sara, Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal 2019-11-26
10303624 Arbitrating and multiplexing circuitry Peter Andrew Riocreux, Alessandro Grande 2019-05-28
10289587 Switching device using buffering Ian David Andrews, Daniel Sara, George Robert Scott Lloyd 2019-05-14
10185667 Storage controller 2019-01-22
10169236 Cache coherency Sean James Salisbury 2019-01-01
9977742 Cache coherency Sean James Salisbury 2018-05-22