Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Daniel Sara — 12 Patents

NVIDIA: 12 patents #582 of 7,811Top 8%
Sheffield, GB: #11 of 655 inventorsTop 2%
Overall (All Time): #396,045 of 4,157,543Top 10%
12 Patents All Time
Daniel Sara has been granted 12 US patents while listed as an inventor at NVIDIA. The first was granted in 2016 and the most recent in August 2025. Daniel Sara ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list Daniel Sara in Sheffield, GB.

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12399735 Managing transaction request identifiers and indicators to control or bypass in-order handling of transaction requests Andrew David Tune, Guanghui Geng 2025-08-26
11314675 Interface circuitry for exchanging information with master, home, and slave nodes using different data transfer protocols Guanghui Geng, Andrew David Tune, Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal 2022-04-26
10489323 Data processing system for a home node to authorize a master to bypass the home node to directly send data to a slave Guanghui Geng, Andrew David Tune, Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal 2019-11-26
10289587 Switching device using buffering Ian David Andrews, Andrew David Tune, George Robert Scott Lloyd 2019-05-14
10078589 Enforcing data protection in an interconnect Antony John Harris, Hakan Persson, Andrew Christopher Rose, Ian Rudolf Bratt 2018-09-18
9928195 Interconnect and method of operation of an interconnect for ordered write observation (OWO) Andrew David Tune, Peter Andrew Riocreux, Sean James Salisbury, George Robert Scott Lloyd 2018-03-27
9892072 Transaction response modification within interconnect circuitry Andrew David Tune, Arthur Brian Laughton, Sean James Salisbury, Peter Andrew Riocreux 2018-02-13
9852088 Hazard checking control within interconnect circuitry Andrew David Tune, Sean James Salisbury, Arthur Brian Laughton, Peter Andrew Riocreux 2017-12-26
9632955 Reorder buffer permitting parallel processing operations with repair on ordering hazard detection within interconnect circuitry Arthur Brian Laughton, Andrew David Tune 2017-04-25
9507716 Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit Sean James Salisbury, Andrew David Tune, Jamshed Jalal, Mark David Werkheiser, Arthur Brian Laughton +2 more 2016-11-29
9442878 Parallel snoop and hazard checking with interconnect circuitry Andrew David Tune 2016-09-13
9311244 Enforcing ordering of snoop transactions in an interconnect for an integrated circuit Sean James Salisbury, Andrew David Tune 2016-04-12 $7,141,000