Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11599467 | Cache for storing coherent and non-coherent data | Jamshed Jalal, Bruce James Mathewson, Tushar P. Ringe, Sean James Salisbury | 2023-03-07 |
| 11537543 | Technique for handling protocol conversion | Ashok Kumar Tummala, Jamshed Jalal, Jeffrey Carl Defilippi, Anitha Kona, Bruce James Mathewson | 2022-12-27 |
| 10078589 | Enforcing data protection in an interconnect | Daniel Sara, Hakan Persson, Andrew Christopher Rose, Ian Rudolf Bratt | 2018-09-18 |
| 9672153 | Memory interface control | Christopher William Laycock, Arthur Brian Laughton | 2017-06-06 |
| 8589631 | Coherency control with writeback ordering | Christopher William Laycock, Bruce James Mathewson, Stuart David Biles | 2013-11-19 |
| 8429457 | Use of statistical representations of traffic flow in a data processing system | Simon Crossley, Alistair Crone Bruce | 2013-04-23 |
| 8375170 | Apparatus and method for handling data in a cache | Christopher William Laycock, Bruce James Mathewson, Andrew Christopher Rose, Richard Roy Grisenthwaite | 2013-02-12 |
| 8275967 | Storage of sequentially sensitive data | — | 2012-09-25 |
| 8190801 | Interconnect logic for a data processing apparatus | Bruce James Mathewson | 2012-05-29 |
| 8045573 | Bit ordering for packetised serial data transmission on an integrated circuit | Bruce James Mathewson | 2011-10-25 |
| 7925840 | Data processing apparatus and method for managing snoop operations | Bruce James Mathewson, Christopher William Laycock | 2011-04-12 |
| 7757027 | Control of master/slave communication within an integrated circuit | Christopher William Laycock, Bruce James Mathewson, Richard Roy Grisenthwaite, Stuart David Biles | 2010-07-13 |
| 7353297 | Handling of write transactions in a data processing apparatus | Bruce James Mathewson | 2008-04-01 |
| 7290075 | Performing arbitration in a data processing apparatus | Alistair Crone Bruce, Bruce James Mathewson | 2007-10-30 |
| 7254658 | Write transaction interleaving | Bruce James Mathewson | 2007-08-07 |
| 7219178 | Bus deadlock avoidance | Bruce James Mathewson, Christopher Wrigley | 2007-05-15 |
| 7213095 | Bus transaction management within data processing systems | Peter Guy Middleton, David John Gwilt, Ian Victor Devereux, Bruce James Mathewson, Richard Roy Grisenthwaite | 2007-05-01 |
| 7213092 | Write response signalling within a communication bus | Bruce James Mathewson | 2007-05-01 |
| 7143221 | Method of arbitrating between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit of a data processing apparatus | Alistair Crone Bruce, Bruce James Mathewson | 2006-11-28 |
| 7117277 | Flexibility of design of a bus interconnect block for a data processing apparatus | Bruce James Mathewson | 2006-10-03 |
| 7069376 | Flexibility of use of a data processing apparatus | Bruce James Mathewson, Dipesh Ishwerbhai Patel | 2006-06-27 |