| 9672153 |
Memory interface control |
Antony John Harris, Arthur Brian Laughton |
2017-06-06 |
| 9477623 |
Barrier transactions in interconnects |
Peter Andrew Riocreux, Bruce James Mathewson, Richard Roy Grisenthwaite |
2016-10-25 |
| 8856408 |
Reduced latency barrier transaction requests in interconnects |
Peter Andrew Riocreux, Bruce James Mathewson, Richard Roy Grisenthwaite |
2014-10-07 |
| 8732400 |
Data store maintenance requests in interconnects |
Peter Andrew Riocreux, Bruce James Mathewson, Richard Roy Grisenthwaite |
2014-05-20 |
| 8607006 |
Barrier transactions in interconnects |
Peter Andrew Riocreux, Bruce James Mathewson, Richard Roy Grisenthwaite |
2013-12-10 |
| 8589631 |
Coherency control with writeback ordering |
Antony John Harris, Bruce James Mathewson, Stuart David Biles |
2013-11-19 |
| 8463966 |
Synchronising activities of various components in a distributed system |
Peter Andrew Riocreux, Bruce James Mathewson, Richard Roy Grisenthwaite |
2013-06-11 |
| 8375170 |
Apparatus and method for handling data in a cache |
Antony John Harris, Bruce James Mathewson, Andrew Christopher Rose, Richard Roy Grisenthwaite |
2013-02-12 |
| 7925840 |
Data processing apparatus and method for managing snoop operations |
Antony John Harris, Bruce James Mathewson |
2011-04-12 |
| 7757027 |
Control of master/slave communication within an integrated circuit |
Antony John Harris, Bruce James Mathewson, Richard Roy Grisenthwaite, Stuart David Biles |
2010-07-13 |