Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12422992 | Increased throughput for writes to memory | Akshay Kumar, Rahul Mathur, Edward M. McCombs, Andrew David Tune, Gaurav Kumar | 2025-09-23 |
| 12174738 | Circuitry and method | Andrew David Tune, Edward M. McCombs | 2024-12-24 |
| 12087353 | Burst read with flexible burst length for on-chip memory | Edward M. McCombs, Andrew David Tune, Rahul Mathur, Hsin-Yu Chen, Phani Raja Bhushan Chalasani | 2024-09-10 |
| 11599467 | Cache for storing coherent and non-coherent data | Jamshed Jalal, Bruce James Mathewson, Tushar P. Ringe, Antony John Harris | 2023-03-07 |
| 11314676 | Apparatus and method for buffered interconnect | Andrew David Tune | 2022-04-26 |
| 11023390 | Resizing circuitry | Eduard Vardanyan | 2021-06-01 |
| 10942878 | Chunking for burst read transactions | Chiranjeev Acharya, Eduard Vardanyan, Premkishore Shivakumar | 2021-03-09 |
| 10938622 | Interconnection network for integrated circuit with fault detection circuitry provided locally to an upstream location | Julian Jose Hilgemberg Pontes, Andrew David Tune | 2021-03-02 |
| 10796040 | Integrated circuit design and fabrication | Zheng Xu, Arthur Brian Laughton, Charles Filip Brej | 2020-10-06 |
| 10740032 | Resource allocation for atomic data access requests | Chiranjeev Acharya, Eduard Vardanyan, Arthur Brian Laughton | 2020-08-11 |
| 10565146 | Interconnect and method of handling supplementary data in an interconnect | Andrew Brian Thomas Hopkins | 2020-02-18 |
| 10437750 | Relative data width indication for read responses routed by an interconnect | Arthur Brian Laughton, Chiranjeev Acharya, Eduard Vardanyan | 2019-10-08 |
| 10372866 | Data processing system to implement wiring/silicon blockages via parameterized cells | Christopher J. Berry, Adam R. Jatkowski, Frank Malgioglio, Ryan M. Nett, Joseph J. Palumbo +1 more | 2019-08-06 |
| 10255103 | Transaction handling | Chiranjeev Acharya, Arthur Brian Laughton | 2019-04-09 |
| 10169236 | Cache coherency | Andrew David Tune | 2019-01-01 |
| 9977742 | Cache coherency | Andrew David Tune | 2018-05-22 |
| 9928195 | Interconnect and method of operation of an interconnect for ordered write observation (OWO) | Andrew David Tune, Peter Andrew Riocreux, Daniel Sara, George Robert Scott Lloyd | 2018-03-27 |
| 9892072 | Transaction response modification within interconnect circuitry | Andrew David Tune, Arthur Brian Laughton, Daniel Sara, Peter Andrew Riocreux | 2018-02-13 |
| 9852088 | Hazard checking control within interconnect circuitry | Andrew David Tune, Daniel Sara, Arthur Brian Laughton, Peter Andrew Riocreux | 2017-12-26 |
| 9727466 | Interconnect and method of managing a snoop filter for an interconnect | Andrew David Tune | 2017-08-08 |
| 9639470 | Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit | Andrew David Tune, Jamshed Jalal, Mark David Werkheiser | 2017-05-02 |
| 9507716 | Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit | Andrew David Tune, Jamshed Jalal, Mark David Werkheiser, Arthur Brian Laughton, George Robert Scott Lloyd +2 more | 2016-11-29 |
| 9361236 | Handling write requests for a data array | Andrew David Tune | 2016-06-07 |
| 9311244 | Enforcing ordering of snoop transactions in an interconnect for an integrated circuit | Andrew David Tune, Daniel Sara | 2016-04-12 |
| 9294301 | Selecting between contending data packets to limit latency differences between sources | Andrew David Tune, Alistair Crone Bruce | 2016-03-22 |