Issued Patents All Time
Showing 25 most recent of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12001774 | Method to cure antenna violations in clock network using jumpers | Amanda Christine Venton, Peter Milton Nasveschuk, Eric Chien Lai | 2024-06-04 |
| 11296093 | Deep trench capacitor distribution | Asaf Regev, Ofer Geva, Amit Amos Atias, Timothy A. Schell | 2022-04-05 |
| 11157586 | Scoping searches within websites | Mark C. Hampton | 2021-10-26 |
| 11074379 | Multi-cycle latch tree synthesis | Lakshmi N. Reddy, Gustavo E. Tellez, Paul G. Villarrubia, Michael H. Wood, Robert Alan Philhower +2 more | 2021-07-27 |
| 10943051 | Metal fill shape removal from selected nets | Jesse Peter Surprise, Gerald Strevig, III, Shawn Kollesar, Chris Aaron Cavitt, Chaobo Li +1 more | 2021-03-09 |
| 10372866 | Data processing system to implement wiring/silicon blockages via parameterized cells | Adam R. Jatkowski, Frank Malgioglio, Ryan M. Nett, Joseph J. Palumbo, Sean James Salisbury +1 more | 2019-08-06 |
| 10229238 | Congestion aware layer promotion | Lakshmi N. Reddy, Sourav Saha | 2019-03-12 |
| 10157255 | Hierarchically aware interior pinning for large synthesis blocks | Matthew Affeldt, Randall J. Darden, Shyam Ramji, Eddy St. Juste | 2018-12-18 |
| 10140414 | Critical region identification | George Antony, Ricardo H. Nigaglioni, Sridhar H. Rangarajan, Sourav Saha, Vinay K. Singh | 2018-11-27 |
| 9934341 | Simulation of modifications to microprocessor design | Chris Aaron Cavitt, Adam P. Matheny, Jose L. Neves, Jesse Peter Surprise, Michael H. Wood | 2018-04-03 |
| 9928322 | Simulation of modifications to microprocessor design | Chris Aaron Cavitt, Adam P. Matheny, Jose L. Neves, Jesse Peter Surprise, Michael H. Wood | 2018-03-27 |
| 9910952 | Hierarchically aware interior pinning for large synthesis blocks | Matthew Affeldt, Randall J. Darden, Shyam Ramji, Eddy St. Juste | 2018-03-06 |
| 9881100 | Scoping searches within websites | Mark C. Hampton | 2018-01-30 |
| 9858377 | Constraint-driven pin optimization for hierarchical design convergence | Randall J. Darden, Adam R. Jatkowski, Joseph J. Palumbo, Shyam Ramji, Sourav Saha +2 more | 2018-01-02 |
| 9798847 | Cross-hierarchy interconnect adjustment for power recovery | Ricardo H. Nigaglioni, Haifeng Qian, Sourav Saha | 2017-10-24 |
| 9734268 | Slack redistribution for additional power recovery | Yiu-Hing Chan, Arjen A. Mets, Charudhattan Nagarajan, Ricardo H. Nigaglioni, Sourav Saha +1 more | 2017-08-15 |
| 9734270 | Control path power adjustment for chip design | Kaustav Guha, Jose L. Neves, Haifeng Qian, Sourav Saha | 2017-08-15 |
| 9715565 | Physical aware technology mapping in synthesis | Pinaki Chakrabarti, Lakshmi N. Reddy, Sourav Saha | 2017-07-25 |
| 9715572 | Hierarchical wire-pin co-optimization | Ajith Kumar M. Chandrasekaran, Randall J. Darden, Shyam Ramji, Sourav Saha | 2017-07-25 |
| 9710585 | Physical aware technology mapping in synthesis | Pinaki Chakrabarti, Lakshmi N. Reddy, Sourav Saha | 2017-07-18 |
| 9703920 | Intra-run design decision process for circuit synthesis | Lakshmi N. Reddy, Sourav Saha, Matthew M. Ziegler | 2017-07-11 |
| 9703910 | Control path power adjustment for chip design | Kaustav Guha, Jose L. Neves, Haifeng Qian, Sourav Saha | 2017-07-11 |
| 9697322 | Hierarchical wire-pin co-optimization | Ajith Kumar M. Chandrasekaran, Randall J. Darden, Shyam Ramji, Sourav Saha | 2017-07-04 |
| 9690900 | Intra-run design decision process for circuit synthesis | Lakshmi N. Reddy, Sourav Saha, Matthew M. Ziegler | 2017-06-27 |
| 9684757 | Cross-hierarchy interconnect adjustment for power recovery | Ricardo H. Nigaglioni, Haifeng Qian, Sourav Saha | 2017-06-20 |