Issued Patents All Time
Showing 25 most recent of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423502 | Rule check heatmap prediction | Rongjian Liang, Hua Xiang, Jinwook Jung, Gi-Joon Nam, Shyam Ramji +2 more | 2025-09-23 |
| 12124789 | Multi-stage electronic design automation parameter tuning | Gi-Joon Nam, Jinwook Jung, Alexey Y. Lvov, Hua Xiang, Rongjian Liang | 2024-10-22 |
| 11983477 | Routing layer re-optimization in physical synthesis | Ying Zhou, Cindy S. Washburn, Alexander J. Suess | 2024-05-14 |
| 11636245 | Methods and systems for leveraging computer-aided design variability in synthesis tuning | Matthew M. Ziegler, Robert L. Franch | 2023-04-25 |
| 11314920 | Time-driven placement and/or cloning of components for an integrated circuit | Woohyun Chung, Gi-Joon Nam | 2022-04-26 |
| 11080443 | Memory element graph-based placement in integrated circuit design | Myung-Chul Kim, Arjen A. Mets, Gi-Joon Nam, Shyam Ramji, Alexander J. Suess +2 more | 2021-08-03 |
| 11074379 | Multi-cycle latch tree synthesis | Gustavo E. Tellez, Paul G. Villarrubia, Christopher J. Berry, Michael H. Wood, Robert Alan Philhower +2 more | 2021-07-27 |
| 10977419 | Time-driven placement and/or cloning of components for an integrated circuit | Woohyun Chung, Gi-Joon Nam | 2021-04-13 |
| 10831979 | Time-driven placement and/or cloning of components for an integrated circuit | Woohyun Chung, Gi-Joon Nam | 2020-11-10 |
| 10671791 | Dynamic microprocessor gate design tool for area/timing margin control | Michael A. Kazda, Arjen A. Mets, Cindy S. Washburn, Nancy Y. Zhou | 2020-06-02 |
| 10558775 | Memory element graph-based placement in integrated circuit design | Myung-Chul Kim, Arjen A. Mets, Gi-Joon Nam, Shyam Ramji, Alexander J. Suess +2 more | 2020-02-11 |
| 10534891 | Time-driven placement and/or cloning of components for an integrated circuit | Woohyun Chung, Gi-Joon Nam | 2020-01-14 |
| 10503841 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Stephen T. Quay, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu | 2019-12-10 |
| 10496764 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Stephen T. Quay, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu | 2019-12-03 |
| 10417375 | Time-driven placement and/or cloning of components for an integrated circuit | Woohyun Chung, Gi-Joon Nam | 2019-09-17 |
| 10372837 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Stephen T. Quay, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu | 2019-08-06 |
| 10372836 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Stephen T. Quay, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu | 2019-08-06 |
| 10346558 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Stephen T. Quay, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu | 2019-07-09 |
| 10229238 | Congestion aware layer promotion | Christopher J. Berry, Sourav Saha | 2019-03-12 |
| 10216882 | Critical path straightening system based on free-space aware and timing driven incremental placement | Jinwook Jung, Frank J. Musante, Gi-Joon Nam, Shyam Ramji, Gustavo E. Tellez +1 more | 2019-02-26 |
| 10078722 | Dynamic microprocessor gate design tool for area/timing margin control | Michael A. Kazda, Arjen A. Mets, Cindy S. Washburn, Nancy Y. Zhou | 2018-09-18 |
| 9715565 | Physical aware technology mapping in synthesis | Christopher J. Berry, Pinaki Chakrabarti, Sourav Saha | 2017-07-25 |
| 9710585 | Physical aware technology mapping in synthesis | Christopher J. Berry, Pinaki Chakrabarti, Sourav Saha | 2017-07-18 |
| 9703920 | Intra-run design decision process for circuit synthesis | Christopher J. Berry, Sourav Saha, Matthew M. Ziegler | 2017-07-11 |
| 9690900 | Intra-run design decision process for circuit synthesis | Christopher J. Berry, Sourav Saha, Matthew M. Ziegler | 2017-06-27 |