Issued Patents All Time
Showing 25 most recent of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10839122 | Automatic layer trait generation and promotion cost computation | Yaoguang Wei, Bijian Chen, Ying Zhou | 2020-11-17 |
| 10831971 | Net layer promotion with swap capability in electronic design | Yaoguang Wei, Bijian Chen, Ying Zhou | 2020-11-10 |
| 10503841 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu | 2019-12-10 |
| 10496764 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu | 2019-12-03 |
| 10372836 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu | 2019-08-06 |
| 10372837 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu | 2019-08-06 |
| 10346558 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu | 2019-07-09 |
| 9875326 | Addressing coupled noise-based violations with buffering in a batch environment | Charles J. Alpert, William E. Dougherty, Jr., Zhuo Li, Ying Zhou | 2018-01-23 |
| 9092591 | Automatic generation of wire tag lists for a metal stack | Charles J. Alpert, Robert M. Averill, III, Eric Jason Fluhr, Zhuo Li, Tuhin Mahmud +3 more | 2015-07-28 |
| 9038009 | Early design cycle optimization | Charles J. Alpert, Robert M. Averill, III, Zhuo Li, Jose L. Neves | 2015-05-19 |
| 8881089 | Physical synthesis optimization with fast metric check | Charles J. Alpert, Glenn R. Bee, Zhuo Li, Tuhin Mahmud, Lakshmi N. Reddy +2 more | 2014-11-04 |
| 8769468 | Automatic generation of wire tag lists for a metal stack | Charles J. Alpert, Robert M. Averill, III, Eric Jason Fluhr, Zhuo Li, Tuhin Mahmud +3 more | 2014-07-01 |
| 8640075 | Early design cycle optimzation | Charles J. Alpert, Robert M. Averill, III, Zhuo Li, Jose L. Neves | 2014-01-28 |
| 8386985 | Timing driven routing in integrated circuit design | Charles J. Alpert, Zhuo Li, Ying Zhou | 2013-02-26 |
| 8365120 | Resolving global coupling timing and slew violations for buffer-dominated designs | Charles J. Alpert, Joachim Clabes, Zhuo Li, Tuhin Mahmud | 2013-01-29 |
| 7895557 | Concurrent buffering and layer assignment in integrated circuit layout | Charles J. Alpert, Zhuo Li, Tuhin Mahmud, Paul G. Villarrubla | 2011-02-22 |
| 7890905 | Slew constrained minimum cost buffering | Charles J. Alpert, Arvind K. Karandikar, Tuhin Mahmud, Chin Ngai Sze | 2011-02-15 |
| 7676780 | Techniques for super fast buffer insertion | Charles J. Alpert, Zhuo Li | 2010-03-09 |
| 7484199 | Buffer insertion to reduce wirelength in VLSI circuits | Charles J. Alpert, Tuhin Mahmud | 2009-01-27 |
| 7448007 | Slew constrained minimum cost buffering | Charles J. Alpert, Arvind K. Karandikar, Tuhin Mahmud, Chin Ngai Sze | 2008-11-04 |
| 7392493 | Techniques for super fast buffer insertion | Charles J. Alpert, Zhuo Li | 2008-06-24 |
| 7299442 | Probabilistic congestion prediction with partial blockages | Charles J. Alpert, Zhuo Li | 2007-11-20 |
| 7137081 | Method and apparatus for performing density-biased buffer insertion in an integrated circuit design | Charles J. Alpert, Milos Hrkic | 2006-11-14 |
| 7127696 | Method and apparatus for generating steiner trees using simultaneous blockage avoidance, delay optimization and design density management | Charles J. Alpert, Rama Gopal Gandham, Milos Hrkic | 2006-10-24 |
| 7065730 | Porosity aware buffered steiner tree construction | Charles J. Alpert, Rama Gopal Gandham, Jiang Hu | 2006-06-20 |