Issued Patents All Time
Showing 1–25 of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12400059 | Logic sharing maximization using non-unique matrix representation | Kwangsoo Han | 2025-08-26 |
| 11868695 | Driver resizing using a transition-based pin capacitance increase margin | Jhih-Rong Gao, Yi-Xiao Ding | 2024-01-09 |
| 11797747 | Identifying redundant logic based on clock gate enable condition | Matthew Eaton, George S. Taylor, James Youren, Ji-Zheng Xu | 2023-10-24 |
| 11734485 | Routing congestion based on fractional via cost and via density | Gracieli Posser, Derong Liu, Mehmet Can Yildiz | 2023-08-22 |
| 11675955 | Routing using rule-based blockage extension | Derong Liu, Gracieli Posser, Mehmet Can Yildiz | 2023-06-13 |
| 11675956 | Pruning redundant buffering solutions using fast timing models | Jhih-Rong Gao, Yi-Xiao Ding | 2023-06-13 |
| 11645441 | Machine-learning based clustering for clock tree synthesis | Bentian Jiang, Natarajan Viswanathan, Yi-Xiao Ding | 2023-05-09 |
| 11625525 | Grouping cells in cell library based on clustering | Natarajan Viswanathan, Vitor Bandeira, Yi-Xiao Ding | 2023-04-11 |
| 11620428 | Post-CTS clock tree restructuring | Andrew Mark Chapman | 2023-04-04 |
| 11526650 | Switching power aware driver resizing by considering net activity in buffering algorithm | Yi-Xiao Ding, Jhih-Rong Gao | 2022-12-13 |
| 11520959 | Pruning of buffering candidates for improved efficiency of evaluation | Yi-Xiao Ding, Jhih-Rong Gao, Sheng-En David Lin | 2022-12-06 |
| 11514222 | Cell-width aware buffer insertion technique for narrow channels | Sheng-En David Lin, Yi-Xiao Ding, Jhih-Rong Gao | 2022-11-29 |
| 11461530 | Circuit design routing based on routing demand adjustment | Mateus Paiva Fogaça, Gracieli Posser, Wing-Kai Chow, Mehmet Can Yildiz | 2022-10-04 |
| 11354480 | Determining clock gates for decloning based on simulation and satisfiability solver | Matthew Eaton, Ji-Zheng Xu, George S. Taylor | 2022-06-07 |
| 11354479 | Post-CTS clock tree restructuring with ripple move | Andrew Mark Chapman | 2022-06-07 |
| 11347923 | Buffering algorithm with maximum cost constraint | Yi-Xiao Ding, Jhih-Rong Gao | 2022-05-31 |
| 11321514 | Macro clock latency computation in multiple iteration clock tree synthesis | Dirk Meyer, Ben Thomas Beaumont | 2022-05-03 |
| 11244099 | Machine-learning based prediction method for iterative clustering during clock tree synthesis | Bentian Jiang, Natarajan Viswanathan, Yi-Xiao Ding | 2022-02-08 |
| 11188702 | Dynamic weighting scheme for local cluster refinement | Bentian Jiang, Natarajan Viswanathan, William Robert Reece | 2021-11-30 |
| 11163929 | Generate clock network using inverting integrated clock gate | William Robert Reece, Thomas Andrew Newton, Ruth Patricia Jackson | 2021-11-02 |
| 11132489 | Layer assignment based on wirelength threshold | Derong Liu, Yi-Xiao Ding, Mehmet Can Yildiz | 2021-09-28 |
| 11132490 | Using negative-edge integrated clock gate in clock network | Ruth Patricia Jackson, William Robert Reece, Thomas Andrew Newton | 2021-09-28 |
| 11080457 | Layer assignment and routing based on resistance or capacitance characteristic | Derong Liu, Yi-Xiao Ding, Mehmet Can Yildiz | 2021-08-03 |
| 11030378 | Track assignment by dynamic programming | Yi-Xiao Ding, Mehmet Can Yildiz | 2021-06-08 |
| 10997352 | Routing congestion based on layer-assigned net and placement blockage | Gracieli Posser, Mehmet Can Yildiz, Wen-Hao Liu, Wing-Kai Chow, Derong Liu | 2021-05-04 |