Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12339701 | Insertion delay and area tradeoff for buffering solution selection in clock tree synthesis | Sheng-En David Lin, Natarajan Viswanathan, Charles J. Alpert | 2025-06-24 |
| 12321193 | Hierarchically-aware buffering for clock structures | Sheng-En David Lin, Natarajan Viswanathan, Charles J. Alpert | 2025-06-03 |
| 12046133 | Detection method of key road-sections based on ricci flow | Haifeng Li, Jian Peng, Penglong Li, Zezhong Ma, Zelie Zhang +8 more | 2024-07-23 |
| 11983751 | Systems and methods for detecting inbound and outbound traffic at a facility | Joseph Duffy, Jiankun Liu, Tianyi Mao, Ryan B. Reagan, Zhichun Xiao +2 more | 2024-05-14 |
| 11868695 | Driver resizing using a transition-based pin capacitance increase margin | Jhih-Rong Gao, Zhuo Li | 2024-01-09 |
| 11675956 | Pruning redundant buffering solutions using fast timing models | Jhih-Rong Gao, Zhuo Li | 2023-06-13 |
| 11645441 | Machine-learning based clustering for clock tree synthesis | Bentian Jiang, Natarajan Viswanathan, Zhuo Li | 2023-05-09 |
| 11625525 | Grouping cells in cell library based on clustering | Zhuo Li, Natarajan Viswanathan, Vitor Bandeira | 2023-04-11 |
| 11526650 | Switching power aware driver resizing by considering net activity in buffering algorithm | Zhuo Li, Jhih-Rong Gao | 2022-12-13 |
| 11520959 | Pruning of buffering candidates for improved efficiency of evaluation | Zhuo Li, Jhih-Rong Gao, Sheng-En David Lin | 2022-12-06 |
| 11514222 | Cell-width aware buffer insertion technique for narrow channels | Sheng-En David Lin, Jhih-Rong Gao, Zhuo Li | 2022-11-29 |
| 11347923 | Buffering algorithm with maximum cost constraint | Zhuo Li, Jhih-Rong Gao | 2022-05-31 |
| 11244099 | Machine-learning based prediction method for iterative clustering during clock tree synthesis | Bentian Jiang, Natarajan Viswanathan, Zhuo Li | 2022-02-08 |
| 11132489 | Layer assignment based on wirelength threshold | Derong Liu, Zhuo Li, Mehmet Can Yildiz | 2021-09-28 |
| 11080457 | Layer assignment and routing based on resistance or capacitance characteristic | Derong Liu, Mehmet Can Yildiz, Zhuo Li | 2021-08-03 |
| 11030378 | Track assignment by dynamic programming | Mehmet Can Yildiz, Zhuo Li | 2021-06-08 |
| 10963620 | Buffer insertion technique to consider edge spacing and stack via design rules | Jhih-Rong Gao, Zhuo Li | 2021-03-30 |
| 10936777 | Unified improvement scoring calculation for rebuffering an integrated circuit design | Jhih-Rong Gao, Zhuo Li | 2021-03-02 |
| 10860764 | Layer assignment technique to improve timing in integrated circuit design | Jhih-Rong Gao, Zhuo Li | 2020-12-08 |
| 10706201 | Circuit design routing using multi-panel track assignment | Mehmet Can Yildiz | 2020-07-07 |
| 10685164 | Circuit design routing based on parallel run length rules | Wing-Kai Chow, Gracieli Posser, Mehmet Can Yildiz, Zhuo Li | 2020-06-16 |
| 10509878 | Systems and methods for routing track assignment | Zhuo Li, Wen-Hao Liu | 2019-12-17 |
| 10402533 | Placement of cells in a multi-level routing tree | William Robert Reece, Thomas Andrew Newton, Charles J. Alpert, Zhuo Li | 2019-09-03 |