WR

William Robert Reece

CS Cadence Design Systems: 11 patents #99 of 2,263Top 5%
Overall (All Time): #411,592 of 4,157,543Top 10%
12
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11188702 Dynamic weighting scheme for local cluster refinement Bentian Jiang, Natarajan Viswanathan, Zhuo Li 2021-11-30
11163929 Generate clock network using inverting integrated clock gate Thomas Andrew Newton, Ruth Patricia Jackson, Zhuo Li 2021-11-02
11132490 Using negative-edge integrated clock gate in clock network Ruth Patricia Jackson, Thomas Andrew Newton, Zhuo Li 2021-09-28
10990721 Delay dependence in physically aware cell cloning Thomas Andrew Newton, Zhuo Li 2021-04-27
10963617 Modifying route topology to fix clock tree violations Andrew Mark Chapman, Natarajan Viswanathan, Mehmet Can Yildiz, Gracieli Posser, Zhuo Li 2021-03-30
10963618 Multi-dimension clock gate design in clock tree synthesis Amin Farshidi, Kwangsoo Han, Thomas Andrew Newton, Zhuo Li 2021-03-30
10740532 Route driven placement of fan-out clock drivers Thomas Andrew Newton, Zhuo Li 2020-08-11
10402522 Region aware clustering Natarajan Viswanathan, Charles J. Alpert, Thomas Andrew Newton 2019-09-03
10402533 Placement of cells in a multi-level routing tree Yi-Xiao Ding, Thomas Andrew Newton, Charles J. Alpert, Zhuo Li 2019-09-03
10318693 Balanced scaled-load clustering Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Thomas Andrew Newton 2019-06-11
10198551 Clock cell library selection Amin Farshidi, Zhuo Li, Charles J. Alpert 2019-02-05
5738232 Clutch adapter to prevent over-tightening an end cap to a fluid reservoir Anthony V. Roberts 1998-04-14