Issued Patents All Time
Showing 25 most recent of 119 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430489 | Restructuring algorithm for including user-specified clock instances in a post-CTS clock tree | Andrew Mark Chapman, Ruth Patricia Jackson | 2025-09-30 |
| 12423501 | Skewing level limited clock tree | Andrew Mark Chapman, Andrew Hall | 2025-09-23 |
| 12423499 | Resistance and capacitance aware preferred layer trimming | Derong Liu, Mehmet Can Yildiz | 2025-09-23 |
| 12393760 | Wire density-aware layer assignment | Derong Liu, Wing-Kai Chow, Gracieli Posser, Mehmet Can Yildiz | 2025-08-19 |
| 12393763 | Timing-based layer assignment | Derong Liu, Wing-Kai Chow, Mehmet Can Yildiz | 2025-08-19 |
| 12339701 | Insertion delay and area tradeoff for buffering solution selection in clock tree synthesis | Yi-Xiao Ding, Sheng-En David Lin, Natarajan Viswanathan | 2025-06-24 |
| 12321193 | Hierarchically-aware buffering for clock structures | Yi-Xiao Ding, Sheng-En David Lin, Natarajan Viswanathan | 2025-06-03 |
| 12061857 | Post-CTS insertion delay and skew target reformulation of clock tree | Andrew Mark Chapman, Andrew Hall | 2024-08-13 |
| 11301757 | Fault-tolerant power-driven synthesis | Pallab Datta, Myron D. Flickner, Zhou Li, Dharmendra S. Modha, Gi-Joon Nam | 2022-04-12 |
| 10796049 | Waveform propagation timing modeling for circuit design | Kwangsoo Han, Zhuo Li | 2020-10-06 |
| 10679120 | Power driven synaptic network synthesis | Pallab Datta, Myron D. Flickner, Zhuo Li, Dharmendra S. Modha, Gi-Joon Nam | 2020-06-09 |
| 10643019 | View pruning for routing tree optimization | Kwangsoo Han, Zhuo Li | 2020-05-05 |
| 10579767 | Systems and methods for routing a clock net with multiple layer ranges | Zhuo Li, Wen-Hao Liu, Gracieli Posser, Ruth Patricia Jackson | 2020-03-03 |
| 10552740 | Fault-tolerant power-driven synthesis | Pallab Datta, Myron D. Flickner, Zhuo Li, Dharmendra S. Modha, Gi-Joon Nam | 2020-02-04 |
| 10460065 | Routing topology generation using spine-like tree structure | Wen-Hao Liu, Wing-Kai Chow, Gracieli Posser, Mehmet Can Yildiz, Zhuo Li | 2019-10-29 |
| 10402522 | Region aware clustering | Natarajan Viswanathan, Thomas Andrew Newton, William Robert Reece | 2019-09-03 |
| 10402533 | Placement of cells in a multi-level routing tree | William Robert Reece, Yi-Xiao Ding, Thomas Andrew Newton, Zhuo Li | 2019-09-03 |
| 10380287 | Systems and methods for modifying a balanced clock structure | Dirk Meyer, Zhuo Li | 2019-08-13 |
| 10354040 | Systems and methods for clock tree generation with buffers and inverters | Amin Farshidi, Thomas Andrew Newton, Zhuo Li | 2019-07-16 |
| 10354183 | Power-driven synthesis under latency constraints | Pallab Datta, Myron D. Flickner, Zhuo Li, Dharmendra S. Modha, Gi-Joon Nam | 2019-07-16 |
| 10318693 | Balanced scaled-load clustering | Natarajan Viswanathan, Zhuo Li, William Robert Reece, Thomas Andrew Newton | 2019-06-11 |
| 10289797 | Local cluster refinement | Natarajan Viswanathan, Wen-Hao Liu, Thomas Andrew Newton | 2019-05-14 |
| 10289795 | Routing tree topology generation | Jhih-Rong Gao, Thomas Andrew Newton, Derong Liu, Mehmet Can Yildiz, Zhuo Li | 2019-05-14 |
| 10289775 | Systems and methods for assigning clock taps based on timing | Brian Wilson, Zhuo Li | 2019-05-14 |
| 10282506 | Systems and methods for clock tree clustering | Dirk Meyer, Zhuo Li | 2019-05-07 |