Issued Patents All Time
Showing 25 most recent of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406186 | Conflict-free, stall-free, broadcast network on chip | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Jun Sawada, Dharmendra S. Modha +2 more | 2025-09-02 |
| 12406174 | Multi-agent instruction execution engine for neural inference processing | Andrew S. Cassidy, Simon James Hollis, Hartmut Penner, Jun Sawada, John V. Arthur | 2025-09-02 |
| 12400109 | Functional synthesis of networks of neurosynaptic cores on neuromorphic substrates | Andrew S. Cassidy, Myron D. Flickner, Dharmendra S. Modha | 2025-08-26 |
| 12400112 | Efficient method for VLSI implementation of useful neural network activation functions | Jun Sawada, Myron D. Flickner, Andrew S. Cassidy, John V. Arthur, Dharmendra S. Modha +6 more | 2025-08-26 |
| 12387082 | Scheduler for mapping neural networks onto an array of neural cores in an inference processing unit | Andrew S. Cassidy, Myron D. Flickner, Hartmut Penner, Rathinakumar Appuswamy, Jun Sawada +5 more | 2025-08-12 |
| 12260316 | Automatic timing resolution among neural network components | Myron D. Flickner, Dharmendra S. Modha | 2025-03-25 |
| 12182687 | Data representation for dynamic precision in neural network cores | John V. Arthur, Andrew S. Cassidy, Myron D. Flickner, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2024-12-31 |
| 12165050 | Networks for distributing parameters and data to neural network compute cores | John V. Arthur, Brian Taba, Rathinakumar Appuswamy, Andrew S. Cassidy, Steven K. Esser +5 more | 2024-12-10 |
| 12067472 | Defect resistant designs for location-sensitive neural network processor arrays | Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner +5 more | 2024-08-20 |
| 12056598 | Runtime reconfigurable neural network processor core | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Steven K. Esser, Myron D. Flickner +5 more | 2024-08-06 |
| 11847553 | Parallel computational architecture with reconfigurable core-level and vector-level parallelism | Andrew S. Cassidy, Myron D. Flickner, Hartmut Penner, Rathinakumar Appuswamy, Jun Sawada +5 more | 2023-12-19 |
| 11663461 | Instruction distribution in an array of neural network cores | Hartmut Penner, Dharmendra S. Modha, John V. Arthur, Andrew S. Cassidy, Rathinakumar Appuswamy +5 more | 2023-05-30 |
| 11645501 | Distributed, event-based computation using neuromorphic cores | Arnon Amir, David J. Berg, Jeffrey A. Kusnitz, Hartmut Penner | 2023-05-09 |
| 11636317 | Long-short term memory (LSTM) cells on spiking neuromorphic hardware | Rathinakumar Appuswamy, Michael Beyeler, Myron D. Flickner, Dharmendra S. Modha | 2023-04-25 |
| 11586893 | Core utilization optimization by dividing computational blocks across cores | Arnon Amir, Nimrod Megiddo, Dharmendra S. Modha | 2023-02-21 |
| 11537859 | Flexible precision neural inference processing unit | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Steve Esser, Myron D. Flickner +4 more | 2022-12-27 |
| 11521085 | Neural network weight distribution from a grid of memory elements | Jun Sawada, Dharmendra S. Modha, Andrew S. Cassidy, John V. Arthur, Tapan K. Nayak +3 more | 2022-12-06 |
| 11501140 | Runtime reconfigurable neural network processor core | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Steven K. Esser, Myron D. Flickner +5 more | 2022-11-15 |
| 11341401 | Hardware architecture for simulating a neural network of neurons | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha | 2022-05-24 |
| 11301757 | Fault-tolerant power-driven synthesis | Charles J. Alpert, Myron D. Flickner, Zhou Li, Dharmendra S. Modha, Gi-Joon Nam | 2022-04-12 |
| 11295203 | Optimizing neuron placement in a neuromorphic system | Rodrigo Alvarez-Icaza, Jeffrey A. Kusnitz | 2022-04-05 |
| 11270196 | Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine | Jun Sawada, Filipp A. Akopyan, Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy +5 more | 2022-03-08 |
| 11263011 | Compound instruction set architecture for a neural inference chip | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Michael Vincent DeBole, Steven K. Esser +5 more | 2022-03-01 |
| 11238347 | Data distribution in an array of neural network cores | Brian Taba, Andrew S. Cassidy, Myron D. Flickner, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2022-02-01 |
| 11205125 | Scheduler and simulator for an area-efficient, reconfigurable, energy-efficient, speed-efficient neural network | Dharmendra S. Modha | 2021-12-21 |