Issued Patents All Time
Showing 25 most recent of 254 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406186 | Conflict-free, stall-free, broadcast network on chip | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Jun Sawada, Michael Vincent DeBole +2 more | 2025-09-02 |
| 12400112 | Efficient method for VLSI implementation of useful neural network activation functions | Jun Sawada, Myron D. Flickner, Andrew S. Cassidy, John V. Arthur, Pallab Datta +6 more | 2025-08-26 |
| 12400109 | Functional synthesis of networks of neurosynaptic cores on neuromorphic substrates | Andrew S. Cassidy, Pallab Datta, Myron D. Flickner | 2025-08-26 |
| 12387082 | Scheduler for mapping neural networks onto an array of neural cores in an inference processing unit | Pallab Datta, Andrew S. Cassidy, Myron D. Flickner, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2025-08-12 |
| 12260316 | Automatic timing resolution among neural network components | Pallab Datta, Myron D. Flickner | 2025-03-25 |
| 12182686 | Neural hardware accelerator for parallel and distributed tensor computations | — | 2024-12-31 |
| 12182687 | Data representation for dynamic precision in neural network cores | John V. Arthur, Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner +5 more | 2024-12-31 |
| 12165050 | Networks for distributing parameters and data to neural network compute cores | John V. Arthur, Brian Taba, Rathinakumar Appuswamy, Andrew S. Cassidy, Pallab Datta +5 more | 2024-12-10 |
| 12067472 | Defect resistant designs for location-sensitive neural network processor arrays | Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Steven K. Esser +5 more | 2024-08-20 |
| 12056598 | Runtime reconfigurable neural network processor core | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Steven K. Esser +5 more | 2024-08-06 |
| 11847553 | Parallel computational architecture with reconfigurable core-level and vector-level parallelism | Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2023-12-19 |
| 11823054 | Learned step size quantization | Steve Esser, Jeffrey L. McKinstry, Deepika Bablani, Rathinakumar Appuswamy | 2023-11-21 |
| 11663461 | Instruction distribution in an array of neural network cores | Hartmut Penner, John V. Arthur, Andrew S. Cassidy, Rathinakumar Appuswamy, Pallab Datta +5 more | 2023-05-30 |
| 11636317 | Long-short term memory (LSTM) cells on spiking neuromorphic hardware | Rathinakumar Appuswamy, Michael Beyeler, Pallab Datta, Myron D. Flickner | 2023-04-25 |
| 11586893 | Core utilization optimization by dividing computational blocks across cores | Arnon Amir, Pallab Datta, Nimrod Megiddo | 2023-02-21 |
| 11580366 | Neuromorphic event-driven neural computing architecture in a scalable neural network | Filipp A. Akopyan, John V. Arthur, Rajit Manohar, Paul A. Merolla, Alyosha Molnar +1 more | 2023-02-14 |
| 11537859 | Flexible precision neural inference processing unit | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Steve Esser +4 more | 2022-12-27 |
| 11521085 | Neural network weight distribution from a grid of memory elements | Jun Sawada, Andrew S. Cassidy, John V. Arthur, Tapan K. Nayak, Carlos O. Otero +3 more | 2022-12-06 |
| 11501140 | Runtime reconfigurable neural network processor core | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Steven K. Esser +5 more | 2022-11-15 |
| 11481621 | Unsupervised, supervised and reinforced learning via spiking computation | — | 2022-10-25 |
| 11410017 | Synaptic, dendritic, somatic, and axonal plasticity in a network of neural cores using a plastic multi-stage crossbar switching | — | 2022-08-09 |
| 11341401 | Hardware architecture for simulating a neural network of neurons | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Paul A. Merolla | 2022-05-24 |
| 11301757 | Fault-tolerant power-driven synthesis | Charles J. Alpert, Pallab Datta, Myron D. Flickner, Zhou Li, Gi-Joon Nam | 2022-04-12 |
| 11295204 | Area-efficient, reconfigurable, energy-efficient, speed-efficient neural network substrate | — | 2022-04-05 |
| 11295201 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network | John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla +3 more | 2022-04-05 |