Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12400112 | Efficient method for VLSI implementation of useful neural network activation functions | Jun Sawada, Myron D. Flickner, Andrew S. Cassidy, John V. Arthur, Pallab Datta +6 more | 2025-08-26 |
| 12387082 | Scheduler for mapping neural networks onto an array of neural cores in an inference processing unit | Pallab Datta, Andrew S. Cassidy, Myron D. Flickner, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2025-08-12 |
| 12182687 | Data representation for dynamic precision in neural network cores | John V. Arthur, Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner +5 more | 2024-12-31 |
| 12165050 | Networks for distributing parameters and data to neural network compute cores | John V. Arthur, Rathinakumar Appuswamy, Andrew S. Cassidy, Pallab Datta, Steven K. Esser +5 more | 2024-12-10 |
| 12067472 | Defect resistant designs for location-sensitive neural network processor arrays | Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Steven K. Esser +5 more | 2024-08-20 |
| 12056598 | Runtime reconfigurable neural network processor core | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Steven K. Esser +5 more | 2024-08-06 |
| 11847553 | Parallel computational architecture with reconfigurable core-level and vector-level parallelism | Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2023-12-19 |
| 11663461 | Instruction distribution in an array of neural network cores | Hartmut Penner, Dharmendra S. Modha, John V. Arthur, Andrew S. Cassidy, Rathinakumar Appuswamy +5 more | 2023-05-30 |
| 11537859 | Flexible precision neural inference processing unit | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Steve Esser +4 more | 2022-12-27 |
| 11521085 | Neural network weight distribution from a grid of memory elements | Jun Sawada, Dharmendra S. Modha, Andrew S. Cassidy, John V. Arthur, Tapan K. Nayak +3 more | 2022-12-06 |
| 11501140 | Runtime reconfigurable neural network processor core | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Steven K. Esser +5 more | 2022-11-15 |
| 11263011 | Compound instruction set architecture for a neural inference chip | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Michael Vincent DeBole +5 more | 2022-03-01 |
| 11238347 | Data distribution in an array of neural network cores | Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2022-02-01 |
| 11010662 | Massively parallel neural inference computing elements | Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Steven K. Esser +5 more | 2021-05-18 |
| 10621489 | Massively parallel neural inference computing elements | Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Steven K. Esser +5 more | 2020-04-14 |
| 9704094 | Mapping of algorithms to neurosynaptic hardware | Arnon Amir, David J. Berg, Pallab Datta, Myron D. Flickner, Paul A. Merolla +2 more | 2017-07-11 |
| 8812413 | Growing simulated biological neural circuits in a simulated physical volume | Paul A. Rhodes | 2014-08-19 |
| 8165971 | Generating simulated neural circuits in a voxel space | Paul A. Rhodes | 2012-04-24 |