Issued Patents All Time
Showing 25 most recent of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406174 | Multi-agent instruction execution engine for neural inference processing | Andrew S. Cassidy, Simon James Hollis, Hartmut Penner, Jun Sawada, Pallab Datta | 2025-09-02 |
| 12406186 | Conflict-free, stall-free, broadcast network on chip | Andrew S. Cassidy, Rathinakumar Appuswamy, Jun Sawada, Dharmendra S. Modha, Michael Vincent DeBole +2 more | 2025-09-02 |
| 12400112 | Efficient method for VLSI implementation of useful neural network activation functions | Jun Sawada, Myron D. Flickner, Andrew S. Cassidy, Pallab Datta, Dharmendra S. Modha +6 more | 2025-08-26 |
| 12387082 | Scheduler for mapping neural networks onto an array of neural cores in an inference processing unit | Pallab Datta, Andrew S. Cassidy, Myron D. Flickner, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2025-08-12 |
| 12182687 | Data representation for dynamic precision in neural network cores | Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2024-12-31 |
| 12165050 | Networks for distributing parameters and data to neural network compute cores | Brian Taba, Rathinakumar Appuswamy, Andrew S. Cassidy, Pallab Datta, Steven K. Esser +5 more | 2024-12-10 |
| 12067472 | Defect resistant designs for location-sensitive neural network processor arrays | Rathinakumar Appuswamy, Andrew S. Cassidy, Pallab Datta, Steven K. Esser, Myron D. Flickner +5 more | 2024-08-20 |
| 12056598 | Runtime reconfigurable neural network processor core | Andrew S. Cassidy, Rathinakumar Appuswamy, Pallab Datta, Steven K. Esser, Myron D. Flickner +5 more | 2024-08-06 |
| 11847553 | Parallel computational architecture with reconfigurable core-level and vector-level parallelism | Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2023-12-19 |
| 11663461 | Instruction distribution in an array of neural network cores | Hartmut Penner, Dharmendra S. Modha, Andrew S. Cassidy, Rathinakumar Appuswamy, Pallab Datta +5 more | 2023-05-30 |
| 11580366 | Neuromorphic event-driven neural computing architecture in a scalable neural network | Filipp A. Akopyan, Rajit Manohar, Paul A. Merolla, Dharmendra S. Modha, Alyosha Molnar +1 more | 2023-02-14 |
| 11537859 | Flexible precision neural inference processing unit | Andrew S. Cassidy, Rathinakumar Appuswamy, Pallab Datta, Steve Esser, Myron D. Flickner +4 more | 2022-12-27 |
| 11521085 | Neural network weight distribution from a grid of memory elements | Jun Sawada, Dharmendra S. Modha, Andrew S. Cassidy, Tapan K. Nayak, Carlos O. Otero +3 more | 2022-12-06 |
| 11501140 | Runtime reconfigurable neural network processor core | Andrew S. Cassidy, Rathinakumar Appuswamy, Pallab Datta, Steven K. Esser, Myron D. Flickner +5 more | 2022-11-15 |
| 11341401 | Hardware architecture for simulating a neural network of neurons | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Pallab Datta, Paul A. Merolla, Dharmendra S. Modha | 2022-05-24 |
| 11295201 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network | Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha +3 more | 2022-04-05 |
| 11270196 | Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine | Jun Sawada, Filipp A. Akopyan, Rathinakumar Appuswamy, Andrew S. Cassidy, Pallab Datta +5 more | 2022-03-08 |
| 11263011 | Compound instruction set architecture for a neural inference chip | Andrew S. Cassidy, Rathinakumar Appuswamy, Pallab Datta, Michael Vincent DeBole, Steven K. Esser +5 more | 2022-03-01 |
| 11238347 | Data distribution in an array of neural network cores | Brian Taba, Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner +5 more | 2022-02-01 |
| 11238343 | Scalable neural hardware for the noisy-OR model of Bayesian networks | Steven K. Esser, Paul A. Merolla, Dharmendra S. Modha | 2022-02-01 |
| 11200496 | Hardware-software co-design of neurosynaptic systems | Pallab Datta, Steven K. Esser, Myron D. Flickner, Dharmendra S. Modha, Tapan K. Nayak | 2021-12-14 |
| 11184221 | Yield tolerance in a neurosynaptic system | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2021-11-23 |
| 11074496 | Providing transposable access to a synapse array using a recursive array layout | John E. Barth, Jr., Paul A. Merolla, Dharmendra S. Modha | 2021-07-27 |
| 11049001 | Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2021-06-29 |
| 11010662 | Massively parallel neural inference computing elements | Rathinakumar Appuswamy, Andrew S. Cassidy, Pallab Datta, Steven K. Esser, Myron D. Flickner +5 more | 2021-05-18 |