Issued Patents All Time
Showing 25 most recent of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12400112 | Efficient method for VLSI implementation of useful neural network activation functions | Jun Sawada, Myron D. Flickner, Andrew S. Cassidy, John V. Arthur, Pallab Datta +6 more | 2025-08-26 |
| 12387082 | Scheduler for mapping neural networks onto an array of neural cores in an inference processing unit | Pallab Datta, Andrew S. Cassidy, Myron D. Flickner, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2025-08-12 |
| 12182687 | Data representation for dynamic precision in neural network cores | John V. Arthur, Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner +5 more | 2024-12-31 |
| 12165050 | Networks for distributing parameters and data to neural network compute cores | John V. Arthur, Brian Taba, Rathinakumar Appuswamy, Andrew S. Cassidy, Pallab Datta +5 more | 2024-12-10 |
| 12067472 | Defect resistant designs for location-sensitive neural network processor arrays | Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Myron D. Flickner +5 more | 2024-08-20 |
| 12056598 | Runtime reconfigurable neural network processor core | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Myron D. Flickner +5 more | 2024-08-06 |
| 11847553 | Parallel computational architecture with reconfigurable core-level and vector-level parallelism | Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2023-12-19 |
| 11663461 | Instruction distribution in an array of neural network cores | Hartmut Penner, Dharmendra S. Modha, John V. Arthur, Andrew S. Cassidy, Rathinakumar Appuswamy +5 more | 2023-05-30 |
| 11556767 | High dynamic range, high class count, high input rate winner-take-all on neuromorphic hardware | Alexander Andreopoulos, Jeffrey A. Kusnitz | 2023-01-17 |
| 11501140 | Runtime reconfigurable neural network processor core | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Myron D. Flickner +5 more | 2022-11-15 |
| 11270196 | Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine | Jun Sawada, Filipp A. Akopyan, Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy +5 more | 2022-03-08 |
| 11263011 | Compound instruction set architecture for a neural inference chip | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Michael Vincent DeBole +5 more | 2022-03-01 |
| 11238347 | Data distribution in an array of neural network cores | Brian Taba, Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner +5 more | 2022-02-01 |
| 11238343 | Scalable neural hardware for the noisy-OR model of Bayesian networks | John V. Arthur, Paul A. Merolla, Dharmendra S. Modha | 2022-02-01 |
| 11227180 | Extracting motion saliency features from video using a neurosynaptic system | Alexander Andreopoulos, Dharmendra S. Modha | 2022-01-18 |
| 11200496 | Hardware-software co-design of neurosynaptic systems | John V. Arthur, Pallab Datta, Myron D. Flickner, Dharmendra S. Modha, Tapan K. Nayak | 2021-12-14 |
| 11138495 | Classifying features using a neurosynaptic system | Rathinakumar Appuswamy, Dharmendra S. Modha | 2021-10-05 |
| 11138492 | Canonical spiking neuron network for spatiotemporal associative memory | Dharmendra S. Modha, Anthony Ndirango | 2021-10-05 |
| 11010662 | Massively parallel neural inference computing elements | Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Myron D. Flickner +5 more | 2021-05-18 |
| 10990872 | Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency | Filipp A. Akopyan, Rodrigo Alvarez-Icaza, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson +3 more | 2021-04-27 |
| 10846567 | Scene understanding using a neurosynaptic system | Alexander Andreopoulos, Rathinakumar Appuswamy, Pallab Datta, Dharmendra S. Modha | 2020-11-24 |
| 10810487 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha +4 more | 2020-10-20 |
| 10769519 | Converting digital numeric data to spike event data | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Myron D. Flickner, Bryan L. Jackson +4 more | 2020-09-08 |
| 10755165 | Converting spike event data to digital numeric data | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Myron D. Flickner, Bryan L. Jackson +4 more | 2020-08-25 |
| 10650309 | High dynamic range, high class count, high input rate winner-take-all on neuromorphic hardware | Alexander Andreopoulos, Jeffrey A. Kusnitz | 2020-05-12 |