Issued Patents All Time
Showing 25 most recent of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11184221 | Yield tolerance in a neurosynaptic system | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha +1 more | 2021-11-23 |
| 11144553 | Streaming programmable point mapper and compute hardware | David J. Berg, Andrew S. Cassidy, Michael Vincent DeBole | 2021-10-12 |
| 11049001 | Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha +1 more | 2021-06-29 |
| 10990872 | Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency | Filipp A. Akopyan, Rodrigo Alvarez-Icaza, John V. Arthur, Andrew S. Cassidy, Steven K. Esser +3 more | 2021-04-27 |
| 10984307 | Peripheral device interconnections for neurosynaptic systems | Filipp A. Akopyan, Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla +2 more | 2021-04-20 |
| 10929747 | Dual deterministic and stochastic neurosynaptic core circuit | Rodrigo Alvarez-Icaza, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha +1 more | 2021-02-23 |
| 10832151 | Implementing stochastic networks using magnetic tunnel junctions | Dharmendra S. Modha | 2020-11-10 |
| 10785745 | Scaling multi-core neurosynaptic networks across chip boundaries | Rodrigo Alvarez Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha +1 more | 2020-09-22 |
| 10769519 | Converting digital numeric data to spike event data | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner +4 more | 2020-09-08 |
| 10755165 | Converting spike event data to digital numeric data | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner +4 more | 2020-08-25 |
| 10740282 | Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer +3 more | 2020-08-11 |
| 10678741 | Coupling parallel event-driven computation with serial computation | Dharmendra S. Modha, Norman J. Pass | 2020-06-09 |
| 10650301 | Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation | Rodrigo Alvarez-Icaza Rivera, Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla +2 more | 2020-05-12 |
| 10454759 | Yield tolerance in a neurosynaptic system | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha +1 more | 2019-10-22 |
| 10410109 | Peripheral device interconnections for neurosynaptic systems | Filipp A. Akopyan, Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla +2 more | 2019-09-10 |
| 10102474 | Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha +1 more | 2018-10-16 |
| 9992057 | Yield tolerance in a neurosynaptic system | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha +1 more | 2018-06-05 |
| 9984324 | Dual deterministic and stochastic neurosynaptic core circuit | Rodrigo Alvarez-Icaza, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha +1 more | 2018-05-29 |
| 9940302 | Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer +3 more | 2018-04-10 |
| 9924490 | Scaling multi-core neurosynaptic networks across chip boundaries | Rodrigo Alvarez Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha +1 more | 2018-03-20 |
| 9886662 | Converting spike event data to digital numeric data | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner +4 more | 2018-02-06 |
| 9881252 | Converting digital numeric data to spike event data | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner +4 more | 2018-01-30 |
| 9852006 | Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits | Filipp A. Akopyan, Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla +2 more | 2017-12-26 |
| 9797946 | Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha +1 more | 2017-10-24 |
| 9792251 | Array of processor core circuits with reversible tiers | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer +3 more | 2017-10-17 |