Issued Patents All Time
Showing 1–25 of 118 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12148748 | On-chip electrostatic discharge sensor | Kannan K. Thankappan, Boris Vaisband | 2024-11-19 |
| 11992686 | Flexible spinal cord stimulators for pain and trauma management through neuromodulation | Bilwaj Gaonkar, Steven L. Moran, Amir Hanna, Luke Macyszyn | 2024-05-28 |
| 11538764 | Flexible and stretchable interconnects for flexible systems | Arsalan Alam, Amir Hanna, Takafumi Fukushima | 2022-12-27 |
| 11257746 | Power distribution within silicon interconnect fabric | Boris Vaisband, Adeel Ahmad Bajwa | 2022-02-22 |
| 11239542 | Network on interconnect fabric and integrated antenna | Boris Vaisband, Adeel Ahmad Bajwa, Arpan Dasgupta, Arsalan Alam | 2022-02-01 |
| 11210373 | Authenticating a hardware chip using an intrinsic chip identifier | Srivatsan Chellappa, Toshiaki Kirihata, Sami Rosenblatt | 2021-12-28 |
| 10930601 | Flexible fan-out wafer level process and structure | Takafumi Fukushima, Adeel Ahmad Bajwa | 2021-02-23 |
| 10740282 | Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Bryan L. Jackson +3 more | 2020-08-11 |
| 10657231 | Providing an authenticating service of a chip | Srivatsan Chellappa, Toshiaki Kirihata, Sami Rosenblatt | 2020-05-19 |
| 10613754 | Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration | Daniel G. Berger, Troy L. Graves-Abe, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke | 2020-04-07 |
| 10585643 | Fine-grained analog memory device based on charge-trapping in high-K gate dielectrics of transistors | Xuefeng Gu | 2020-03-10 |
| 10503402 | Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration | Daniel G. Berger, Troy L. Graves-Abe, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke | 2019-12-10 |
| 10461067 | Thermally enhanced package to reduce thermal interaction between dies | Janak G. Patel, Daniel G. Berger | 2019-10-29 |
| 10262119 | Providing an authenticating service of a chip | Srivatsan Chellappa, Toshiaki Kirihata, Sami Rosenblatt | 2019-04-16 |
| 10176063 | Faulty core recovery mechanisms for a three-dimensional network on a processor array | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Paul A. Merolla +1 more | 2019-01-08 |
| 9940302 | Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Bryan L. Jackson +3 more | 2018-04-10 |
| 9886193 | Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration | Daniel G. Berger, Troy L. Graves-Abe, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke | 2018-02-06 |
| 9859262 | Thermally enhanced package to reduce thermal interaction between dies | Janak G. Patel, Daniel G. Berger | 2018-01-02 |
| 9792251 | Array of processor core circuits with reversible tiers | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Bryan L. Jackson +3 more | 2017-10-17 |
| 9748114 | Method for forming through silicon via in N+ epitaxy wafers with reduced parasitic capacitance | Kangguo Cheng, Pranita Kerber, Ali Khakifirooz | 2017-08-29 |
| 9690927 | Providing an authenticating service of a chip | Srivatsan Chellappa, Toshiaki Kirihata, Sami Rosenblatt | 2017-06-27 |
| 9588937 | Array of processor core circuits with reversible tiers | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Bryan L. Jackson +3 more | 2017-03-07 |
| 9543229 | Combination of TSV and back side wiring in 3D integration | Pooja R. Batra, John W. Golz, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel | 2017-01-10 |
| 9536809 | Combination of TSV and back side wiring in 3D integration | Pooja R. Batra, John W. Golz, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel | 2017-01-03 |
| 9466538 | Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process | Spyridon Skordas, Donald F. Canaperi, Shidong Li, Wei Lin | 2016-10-11 |