Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10613754 | Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration | Daniel G. Berger, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke | 2020-04-07 |
| 10503402 | Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration | Daniel G. Berger, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke | 2019-12-10 |
| 10296698 | Forming multi-sized through-silicon-via (TSV) structures | Mukta G. Farooq | 2019-05-21 |
| 10170337 | Implant after through-silicon via (TSV) etch to getter mobile ions | Christopher N. Collins, Mukta G. Farooq, Brian J. Greene, Robert Hannon, Herbert L. Ho +1 more | 2019-01-01 |
| 9886193 | Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration | Daniel G. Berger, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke | 2018-02-06 |
| 9640514 | Wafer bonding using boron and nitrogen based bonding stack | Wei Lin, Donald F. Canaperi, Spyridon Skordas, Matthew T. Shoudy, Binglin Miao +2 more | 2017-05-02 |
| 9476927 | Structure and method to determine through silicon via build integrity | Chandrasekharan Kothandaraman, Conal E. Murray | 2016-10-25 |
| 9263324 | 3-D integration using multi stage vias | Mukta G. Farooq | 2016-02-16 |
| 9257336 | Bottom-up plating of through-substrate vias | Mukta G. Farooq, John A. Fitzsimmons | 2016-02-09 |
| 9252133 | Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures | Christopher N. Collins, Mukta G. Farooq, Joyce C. Liu, Gerd Pfeiffer, Thuy L. Tran-Quinn | 2016-02-02 |
| 9214435 | Via structure for three-dimensional circuit integration | Mukta G. Farooq, Spyridon Skordas, Kevin R. Winstel | 2015-12-15 |
| 9060457 | Sidewalls of electroplated copper interconnects | Mukta G. Farooq, John A. Fitzsimmons | 2015-06-16 |
| 9055703 | Sidewalls of electroplated copper interconnects | Mukta G. Farooq, John A. Fitzsimmons | 2015-06-09 |
| 9040407 | Sidewalls of electroplated copper interconnects | Mukta G. Farooq, John A. Fitzsimmons | 2015-05-26 |
| 8975910 | Through-silicon-via with sacrificial dielectric line | Benjamin Himmel, Chandrasekharan Kothandaraman, Norman W. Robson | 2015-03-10 |
| 8956973 | Bottom-up plating of through-substrate vias | Mukta G. Farooq, John A. Fitzsimmons | 2015-02-17 |
| 8951906 | Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via | Mukta G. Farooq | 2015-02-10 |
| 8927427 | Anticipatory implant for TSV | Brian J. Greene, Chandrasekharan Kothandaraman | 2015-01-06 |
| 8907494 | Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures | Christopher N. Collins, Mukta G. Farooq, Joyce C. Liu, Gerd Pfeiffer, Thuy L. Tran-Quinn | 2014-12-09 |
| 8889542 | Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via | Mukta G. Farooq | 2014-11-18 |
| 8853857 | 3-D integration using multi stage vias | Mukta G. Farooq | 2014-10-07 |
| 8791005 | Sidewalls of electroplated copper interconnects | Mukta G. Farooq, John A. Fitzsimmons | 2014-07-29 |
| 8791009 | Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via | Mukta G. Farooq | 2014-07-29 |
| 8691691 | TSV pillar as an interconnecting structure | Mukta G. Farooq, William Francis Landers, Kevin S. Petrarca, Richard P. Volant | 2014-04-08 |
| 8546961 | Alignment marks to enable 3D integration | Mukta G. Farooq, Robert Hannon, Emily R. Kinser, William Francis Landers, Kevin S. Petrarca +2 more | 2013-10-01 |