Issued Patents All Time
Showing 1–25 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9673095 | Protected through semiconductor via (TSV) | Mukta G. Farooq, Jennifer A. Oakley, Kevin S. Petrarca | 2017-06-06 |
| 9401323 | Protected through semiconductor via (TSV) | Mukta G. Farooq, Jennifer A. Oakley, Kevin S. Petrarca | 2016-07-26 |
| 9151781 | Yield enhancement for stacked chips through rotationally-connecting-interposer | Oleg Gluschenkov, Muthukumarasamy Karthikeyan, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang | 2015-10-06 |
| 9040418 | Enhanced capture pads for through semiconductor vias | Mukta G. Farooq, John A. Griesemer, Gary LaFontant, Kevin S. Petrarca | 2015-05-26 |
| 8970011 | Method and structure of forming backside through silicon via connections | Mukta G. Farooq | 2015-03-03 |
| 8894800 | Polymeric edge seal for bonded substrates | Mutka G. Farooq, Thomas Houghton, Nitin Parbhoo | 2014-11-25 |
| 8772949 | Enhanced capture pads for through semiconductor vias | Mukta G. Farooq, John A. Griesemer, Gary LaFontant, Kevin S. Petrarca | 2014-07-08 |
| 8709936 | Method and structure of forming backside through silicon via connections | Mukta G. Farooq | 2014-04-29 |
| 8691691 | TSV pillar as an interconnecting structure | Mukta G. Farooq, Troy L. Graves-Abe, William Francis Landers, Kevin S. Petrarca | 2014-04-08 |
| 8679971 | Metal-contamination-free through-substrate via structure | Mukta G. Farooq, Robert Hannon | 2014-03-25 |
| 8668834 | Protecting a mold having a substantially planar surface provided with a plurality of mold cavities | Bradley P. Jones, Sarah H. Knickerbocker | 2014-03-11 |
| 8658535 | Optimized annular copper TSV | Paul S. Andry, Mukta G. Rarooq, Robert Hannon, Subramanian S. Iyer, Emily R. Kinser +1 more | 2014-02-25 |
| 8633580 | Integrated void fill for through silicon via | Mukta G. Farooq, Kevin S. Petrarca | 2014-01-21 |
| 8613996 | Polymeric edge seal for bonded substrates | Mukta G. Farooq, Thomas Houghton, Nitin Parbhoo | 2013-12-24 |
| 8609537 | Integrated void fill for through silicon via | Mukta G. Farooq, Kevin S. Petrarca | 2013-12-17 |
| 8563403 | Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last | Mukta G. Farooq, Spyridon Skordas, Kevin R. Winstel | 2013-10-22 |
| 8546961 | Alignment marks to enable 3D integration | Mukta G. Farooq, Troy L. Graves-Abe, Robert Hannon, Emily R. Kinser, William Francis Landers +2 more | 2013-10-01 |
| 8492878 | Metal-contamination-free through-substrate via structure | Mukta G. Farooq, Robert Hannon | 2013-07-23 |
| 8487425 | Optimized annular copper TSV | Paul S. Andry, Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Emily R. Kinser +1 more | 2013-07-16 |
| 8455356 | Integrated void fill for through silicon via | Mukta G. Farooq, Kevin S. Petrarca | 2013-06-04 |
| 8394715 | Method of fabricating coaxial through-silicon via | Mukta G. Farooq, Paul F. Findeis, Kevin S. Petrarca | 2013-03-12 |
| 8386977 | Circuit design checking for three dimensional chip technology | Mukta G. Farooq, John A. Griesemer, William Francis Landers, Kevin S. Petrarca | 2013-02-26 |
| 8242604 | Coaxial through-silicon via | Mukta G. Farooq, Paul F. Findeis, Kevin S. Petrarca | 2012-08-14 |
| 8159247 | Yield enhancement for stacked chips through rotationally-connecting-interposer | Oleg Gluschenkov, Muthukumarasamy Karthikeyan, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang | 2012-04-17 |
| 8114707 | Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip | Mukta G. Farooq, Kevin S. Petrarca | 2012-02-14 |