KP

Kevin S. Petrarca

IBM: 120 patents #414 of 70,183Top 1%
📍 Newburgh, NY: #2 of 198 inventorsTop 2%
🗺 New York: #383 of 115,490 inventorsTop 1%
Overall (All Time): #9,954 of 4,157,543Top 1%
120
Patents All Time

Issued Patents All Time

Showing 1–25 of 120 patents

Patent #TitleCo-InventorsDate
12406930 Structure containing a via-to-buried power rail contact structure or a via-to-backside power rail contact structure Ruilong Xie, Stuart A. Sieg, Eric R. Miller 2025-09-02
12178142 Layered substrate structures with aligned optical access to electrical devices Stephen M. Gates, Russell A. Budd, Vivekananda P. Adiga, Douglas M. Gill 2024-12-24
12033981 Create a protected layer for interconnects and devices in a packaged quantum structure David W. Abraham, Oliver Dial, John M. Cotte 2024-07-09
10784200 Ionizing radiation blocking in IC chip to reduce soft errors Mukta G. Farooq, Ian D. Melville, Kenneth P. Rodbell 2020-09-22
10079175 Insulating a via in a semiconductor substrate Mukta G. Farooq, Jennifer A. Oakley, Nicole R. Reardon, Andrew H. Simon 2018-09-18
9824925 Flip chip alignment mark exposing method enabling wafer level underfill Mukta G. Farooq, Nicholas A. Polomoff, Katsuyuki Sakuma 2017-11-21
9728450 Insulating a via in a semiconductor substrate Mukta G. Farooq, Jennifer A. Oakley, Nicole R. Reardon, Andrew H. Simon 2017-08-08
9673095 Protected through semiconductor via (TSV) Mukta G. Farooq, Jennifer A. Oakley, Richard P. Volant 2017-06-06
9511918 Self-locking container Ira L. Allen, Lawrence A. Clevenger, Carl Radens 2016-12-06
9401323 Protected through semiconductor via (TSV) Mukta G. Farooq, Jennifer A. Oakley, Richard P. Volant 2016-07-26
9293375 Selectively grown self-aligned fins for deep isolation integration Stuart A. Sieg, Theodorus E. Standaert 2016-03-22
9093503 Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure Fen Chen, Mukta G. Farooq, Jeffrey P. Gambino, Zhong-Xiang He, Anthony K. Stamper 2015-07-28
9040418 Enhanced capture pads for through semiconductor vias Mukta G. Farooq, John A. Griesemer, Gary LaFontant, Richard P. Volant 2015-05-26
9030295 RFID tag with environmental sensor Ira L. Allen, Lawrence A. Clevenger, Carl Radens 2015-05-12
8999764 Ionizing radiation blocking in IC chip to reduce soft errors Mukta G. Farooq, Ian D. Melville, Kenneth P. Rodbell 2015-04-07
8822141 Front side wafer ID processing Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Stuart A. Sieg 2014-09-02
8815475 Reticle carrier Donald F. Canaperi, Mahadevaiyer Krishnan, Rebecca D. Mih, Steven E. Steen, Henry Grabarz +1 more 2014-08-26
8802990 Self-aligned nano-scale device with parallel plate electrodes Lawrence A. Clevenger, Zhengwen Li, Roger A. Quon, Carl Radens, Brian C. Sapp 2014-08-12
8792080 Method and system to predict lithography focus error using simulated or measured topography Brian C. Sapp, Choongyeun Cho, Lawrence A. Clevenger, Laertis Economikos, Bernhard R. Liegl +1 more 2014-07-29
8772949 Enhanced capture pads for through semiconductor vias Mukta G. Farooq, John A. Griesemer, Gary LaFontant, Richard P. Volant 2014-07-08
8692649 Asset management infrastructure Lawrence A. Clevenger, Rainer Krause, Carl Radens, Brian C. Sapp 2014-04-08
8691691 TSV pillar as an interconnecting structure Mukta G. Farooq, Troy L. Graves-Abe, William Francis Landers, Richard P. Volant 2014-04-08
8665575 Solar module with overheat protection Lawrence A. Clevenger, Harold J. Hovel, Rainer Krause, Zhengwen Li, Gerd Pfeiffer +3 more 2014-03-04
8633580 Integrated void fill for through silicon via Richard P. Volant, Mukta G. Farooq 2014-01-21
8614115 Photovoltaic solar cell device manufacture Lawrence A. Clevenger, Harold J. Hovel, Rainer Krause, Gerd Pfeiffer, Kevin M. Prettyman +2 more 2013-12-24