Issued Patents All Time
Showing 26–50 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8609537 | Integrated void fill for through silicon via | Richard P. Volant, Mukta G. Farooq | 2013-12-17 |
| 8574950 | Electrically contactable grids manufacture | Lawrence A. Clevenger, Rainer Krause, Zhengwen Li, Roger A. Quon, Carl Radens +1 more | 2013-11-05 |
| 8546961 | Alignment marks to enable 3D integration | Mukta G. Farooq, Troy L. Graves-Abe, Robert Hannon, Emily R. Kinser, William Francis Landers +2 more | 2013-10-01 |
| 8535970 | Manufacturing process for making photovoltaic solar cells | Ranier Krauser, Lawrence A. Clevenger, Kevin M. Prettyman, Brian C. Sapp, Harold J. Hovel +3 more | 2013-09-17 |
| 8486751 | Method of manufacturing a photovoltaic cell | Lawrence A. Clevenger, Harold J. Hovel, Rainer Krause, Gerd Pfeiffer, Kevin M. Prettyman +1 more | 2013-07-16 |
| 8476530 | Self-aligned nano-scale device with parallel plate electrodes | Lawrence A. Clevenger, Zhengwen Li, Roger A. Quon, Carl Radens, Brian C. Sapp | 2013-07-02 |
| 8455356 | Integrated void fill for through silicon via | Richard P. Volant, Mukta G. Farooq | 2013-06-04 |
| 8445374 | Soft error rate mitigation by interconnect structure | Mukta G. Farooq, Ian D. Melville | 2013-05-21 |
| 8439728 | Reticle carrier | Donald F. Canaperi, Mahadevaiyer Krishnan, Rebecca D. Mih, Steven E. Steen, Henry Grabarz +1 more | 2013-05-14 |
| 8394715 | Method of fabricating coaxial through-silicon via | Richard P. Volant, Mukta G. Farooq, Paul F. Findeis | 2013-03-12 |
| 8386977 | Circuit design checking for three dimensional chip technology | Mukta G. Farooq, John A. Griesemer, William Francis Landers, Richard P. Volant | 2013-02-26 |
| 8367544 | Self-aligned patterned etch stop layers for semiconductor devices | Kangguo Cheng, Lawrence A. Clevenger, Johnathan E. Faltermeier, Stephan Grunow, Kaushik A. Kumar | 2013-02-05 |
| 8350359 | Semiconductor device using an aluminum interconnect to form through-silicon vias | Matthew S. Angyal, Lawrence A. Clevenger, Carl Radens, Brian C. Sapp | 2013-01-08 |
| 8349729 | Hybrid bonding interface for 3-dimensional chip integration | Karl W. Barth, Ricardo A. Donaton, Spyridon Galis, Shahab Siddiqui | 2013-01-08 |
| 8242604 | Coaxial through-silicon via | Richard P. Volant, Mukta G. Farooq, Paul F. Findeis | 2012-08-14 |
| 8236655 | Fuse link structures using film stress for programming and methods of manufacture | Karl W. Barth, Jeffrey P. Gambino, Tom C. Lee | 2012-08-07 |
| 8159060 | Hybrid bonding interface for 3-dimensional chip integration | Karl W. Barth, Ricardo A. Donaton, Spyridon Galis, Shahab Siddiqui | 2012-04-17 |
| 8120175 | Soft error rate mitigation by interconnect structure | Mukta G. Farooq, Ian D. Melville | 2012-02-21 |
| 8114707 | Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip | Mukta G. Farooq, Richard P. Volant | 2012-02-14 |
| 8110321 | Method of manufacture of damascene reticle | Donald F. Canaperi, Mahadevaiyer Krishnan, Rebecca D. Mih, Steven E. Steen, Henry Grabarz +1 more | 2012-02-07 |
| 8089105 | Fuse link structures using film stress for programming and methods of manufacture | Karl W. Barth, Jeffrey P. Gambino, Tom C. Lee | 2012-01-03 |
| 8017997 | Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via | Ramachandra Divakaruni, Mukta G. Farooq, Jeffrey P. Gambino | 2011-09-13 |
| 7977032 | Method to create region specific exposure in a layer | Christos D. Dimitrakopoulos, Daniel C. Edelstein, Vincent J. McGahay, Satyanarayana V. Nitta, Shom Ponoth +1 more | 2011-07-12 |
| 7943412 | Low temperature Bi-CMOS compatible process for MEMS RF resonators and filters | Leena Paivikki Buchwalter, Kevin K. Chan, Timothy J. Dalton, Christopher V. Jahnes, Jennifer Lund +2 more | 2011-05-17 |
| 7892926 | Fuse link structures using film stress for programming and methods of manufacture | Karl W. Barth, Jeffrey P. Gambino, Tom C. Lee | 2011-02-22 |