Issued Patents All Time
Showing 25 most recent of 220 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431408 | TSV and backside power distribution structure | Ruilong Xie | 2025-09-30 |
| 12300615 | Infrared debond damage mitigation by copper fill pattern | Qianwen Chen, Shahid Butt, Eric D. Perfecto, Michael P. Belyansky, Katsuyuki Sakuma +1 more | 2025-05-13 |
| 12199059 | Sintering a nanoparticle paste for semiconductor chip join | Katsuyuki Sakuma | 2025-01-14 |
| 12106969 | Substrate thinning for a backside power distribution network | Ruilong Xie, Balasubramanian Pranatharthiharan, Julien Frougier, Takeshi Nogami, Roy R. Yu +1 more | 2024-10-01 |
| 12057371 | Semiconductor device with early buried power rail (BPR) and backside power distribution network (BSPDN) | Ruilong Xie, Balasubramanian Pranatharthiharan, Brent A. Anderson | 2024-08-06 |
| 12015003 | High density interconnection and wiring layers, package structures, and integration methods | John U. Knickerbocker, Katsuyuki Sakuma | 2024-06-18 |
| 11984401 | Stacked FET integration with BSPDN | Ruilong Xie, Junli Wang, Dechao Guo | 2024-05-14 |
| 11973058 | Multiple die assembly | Katsuyuki Sakuma, John U. Knickerbocker | 2024-04-30 |
| 11887956 | Temperature hierarchy solder bonding | Katsuyuki Sakuma | 2024-01-30 |
| 11848273 | Bridge chip with through via | James J. Kelly | 2023-12-19 |
| 11824037 | Assembly of a chip to a substrate | Katsuyuki Sakuma, Paul S. Andry, Russell Kastberg | 2023-11-21 |
| 11817394 | Semiconductor circuit power delivery | Katsuyuki Sakuma | 2023-11-14 |
| 11791326 | Memory and logic chip stack with a translator chip | Arvind Kumar, Ravi Nair | 2023-10-17 |
| 11682640 | Protective surface layer on under bump metallurgy for solder joining | James J. Kelly | 2023-06-20 |
| 11545444 | Mitigating cooldown peeling stress during chip package assembly | Katsuyuki Sakuma, Krishna R. Tunga, Hilton T. Toy | 2023-01-03 |
| 11404379 | Structure and method for bridge chip assembly with capillary underfill | Katsuyuki Sakuma | 2022-08-02 |
| 11355379 | Oxide-bonded wafer pair separation using laser debonding | Dale Curtis McHerron, Spyridon Skordas | 2022-06-07 |
| 11315831 | Dual redistribution layer structure | James J. Kelly | 2022-04-26 |
| 11282716 | Integration structure and planar joining | James J. Kelly | 2022-03-22 |
| 11239167 | Cu—Cu bonding for interconnects on bridge chip attached to chips and packaging substrate | Ravi K. Bonam, James J. Kelly, Spyridon Skordas | 2022-02-01 |
| 11211378 | Heterogeneous integration structure for artificial intelligence computing | Arvind Kumar | 2021-12-28 |
| 11171006 | Simultaneous plating of varying size features on semiconductor substrate | James J. Kelly | 2021-11-09 |
| 11049844 | Semiconductor wafer having trenches with varied dimensions for multi-chip modules | Ravi K. Bonam, Dinesh Gupta, James J. Kelly, Kamal K. Sikka, Joshua M. Rubin | 2021-06-29 |
| 10943883 | Planar wafer level fan-out of multi-chip modules having different size chips | Ravi K. Bonam, Dinesh Gupta, James J. Kelly | 2021-03-09 |
| 10923427 | SOI wafers with buried dielectric layers to prevent CU diffusion | Anthony K. Stamper, John A. Fitzsimmons | 2021-02-16 |