Issued Patents All Time
Showing 25 most recent of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12182576 | Executing a composite scalar-vector VLIW instruction having a repeat field | Bruce M. Fleischer, Thomas W. Fox, Arpith Chacko Jacob, Hans M. Jacobson, Kevin O'Brien +1 more | 2024-12-31 |
| 12094525 | Multichannel memory to augment local memory | Swagath Venkataramani, Vijayalakshmi Srinivasan, Arvind Kumar | 2024-09-17 |
| 11791326 | Memory and logic chip stack with a translator chip | Mukta G. Farooq, Arvind Kumar | 2023-10-17 |
| 11574249 | Streamlining data processing optimizations for machine learning workloads | Qi Zhang, Petr Novotny, Hong Min, Shyam Ramji, Lei Yu +2 more | 2023-02-07 |
| 11552243 | MRAM structure with ternary weight storage | Alexander Reznicek, Bahman Hekmatshoartabari, Michael Rizzolo | 2023-01-10 |
| 11461645 | Initialization of memory networks | Bahman Hekmatshoartabari | 2022-10-04 |
| 11328221 | Hybrid model for short text classification with imbalanced data | Yang Yu, Ming Tan, Haoyu Wang, Saloni Potdar | 2022-05-10 |
| 11288208 | Access of named data elements in coordination namespace | Charles Ray Johns, James A. Kahle, Changhoan Kim, Constantinos Evangelinos, Patrick D. Siegl | 2022-03-29 |
| 11275614 | Dynamic update of the number of architected registers assigned to software threads using spill counts | Harold W. Cain, III, Hubertus Franke, Charles Ray Johns, Hung Q. Le, James Allan Kahle | 2022-03-15 |
| 11144231 | Relocation and persistence of named data elements in coordination namespace | Charles Ray Johns, James A. Kahle, Constantinos Evangelinos | 2021-10-12 |
| 11068612 | Microarchitectural techniques to mitigate cache-based data security vulnerabilities | Prashant Jayaprakash Nair, Seokin Hong, Alper Buyuktosunoglu | 2021-07-20 |
| 11016908 | Distributed directory of named data elements in coordination namespace | Charles Ray Johns, James A. Kahle, James C. Sexton | 2021-05-25 |
| 10915460 | Coordination namespace processing | Charles Ray Johns, James A. Kahle, Changhoan Kim, Jose R. Brunheroto, Constantinos Evangelinos +2 more | 2021-02-09 |
| 10831537 | Dynamic update of the number of architected registers assigned to software threads using spill counts | Harold W. Cain, III, Hubertus Franke, Charles Ray Johns, Hung Q. Le | 2020-11-10 |
| 10824481 | Partial synchronization between compute tasks based on threshold specification in a computing system | Zehra N. Sura, Li Zhang, Ashish Kundu | 2020-11-03 |
| 10684958 | Locating node of named data elements in coordination namespace | Charles Ray Johns | 2020-06-16 |
| 10572263 | Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution | Bruce M. Fleischer, Thomas W. Fox, Arpith Chacko Jacob, Hans M. Jacobson, Kevin O'Brien +1 more | 2020-02-25 |
| 10338931 | Approximate synchronization for parallel deep learning | Suyog Gupta | 2019-07-02 |
| 10120810 | Implementing selective cache injection | Philip Heidelberger, Hillery C. Hunter, James A. Kahle | 2018-11-06 |
| 10049061 | Active memory device gather, scatter, and filter | Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, James Allan Kahle, Jaime Moreno | 2018-08-14 |
| 10007242 | Mechanism for controlling subset of devices | Thomas W. Fox, Hans M. Jacobson, Bryan S. Rosenburg | 2018-06-26 |
| 9928190 | High bandwidth low latency data exchange between processing elements | Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson | 2018-03-27 |
| 9910802 | High bandwidth low latency data exchange between processing elements | Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson | 2018-03-06 |
| 9910783 | Implementing selective cache injection | Philip Heidelberger, Hillery C. Hunter, James A. Kahle | 2018-03-06 |
| 9870340 | Multithreading in vector processors | Constantinos Evangelinos, Changhoan Kim | 2018-01-16 |