Issued Patents All Time
Showing 1–25 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12399743 | Padding input data for artificial intelligence accelerators | Cedric Lichtenau, Sunil K. Shukla, Swagath Venkataramani, Kailash Gopalakrishnan, Holger Horbach +4 more | 2025-08-26 |
| 12236338 | Single function to perform combined matrix multiplication and bias add operations | Cedric Lichtenau, Kailash Gopalakrishnan, Sunil K. Shukla, Swagath Venkataramani | 2025-02-25 |
| 12141513 | Method to map convolutional layers of deep neural network on a plurality of processing elements with SIMD execution units, private memories, and connected as a 2D systolic processor array | Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Swagath Venkataramani, Jintao Zhang | 2024-11-12 |
| 12094525 | Multichannel memory to augment local memory | Ravi Nair, Swagath Venkataramani, Arvind Kumar | 2024-09-17 |
| 12056594 | Low precision deep neural network enabled by compensation instructions | Swagath Venkataramani, Shubham Jain, Jungwook Choi, Leland Chang | 2024-08-06 |
| 11941111 | Exploiting fine-grained structured weight sparsity in systolic arrays | Sanchari Sen, Swagath Venkataramani, Kailash Gopalakrishnan, Sunil K. Shukla | 2024-03-26 |
| 11831467 | Programmable multicast protocol for ring-topology based artificial intelligence systems | Shubham Jain, Swagath Venkataramani, Sunil K. Shukla, Martin A Lutz | 2023-11-28 |
| 11669489 | Sparse systolic array design | Swagath Venkataramani, Sanchari Sen, Ankur Agrawal, Sunil K. Shukla, Bruce M. Fleischer +1 more | 2023-06-06 |
| 11620132 | Reusing an operand received from a first-in-first-out (FIFO) buffer according to an operand specifier value specified in a predefined field of an instruction | Bruce M. Fleischer, Sunil K. Shukla, Jungwook Choi | 2023-04-04 |
| 11556450 | Hybrid data-model parallelism for efficient deep learning | Swagath Venkataramani, Philip Heidelberger | 2023-01-17 |
| 11551054 | System-aware selective quantization for performance optimized distributed deep learning | Jungwook Choi, Swagath Venkataramani, Kailash Gopalakrishnan | 2023-01-10 |
| 11354573 | Dynamically resizing minibatch in neural network execution | Swagath Venkataramani, Jungwook Choi | 2022-06-07 |
| 11347517 | Reduced precision based programmable and SIMD dataflow architecture | Kailash Gopalakrishnan, Sunil K. Shukla, Jungwook Choi, Silvia M. Mueller, Bruce M. Fleischer +2 more | 2022-05-31 |
| 11263518 | Bi-scaled deep neural networks | Swagath Venkataramani, Shubham Jain, Leland Chang | 2022-03-01 |
| 11188820 | Deep neural network performance analysis on shared memory accelerator systems | Jungwook Choi, Swagath Venkataramani | 2021-11-30 |
| 11138010 | Loop management in multi-processor dataflow architecture | Chia-Yu Chen, Jungwook Choi, Brian W. Curran, Bruce M. Fleischer, Kailash Gopalakrishnan +2 more | 2021-10-05 |
| 10963387 | Methods of cache preloading on a partition or a context switch | Harold W. Cain, III, Jason D. Zebchuk | 2021-03-30 |
| 10936319 | Predicting cache misses using data access behavior and instruction address | Brian R. Prasky | 2021-03-02 |
| 10838868 | Programmable data delivery by load and store agents on a processing chip interfacing with on-chip memory components and directing data to external memory components | Chia-Yu Chen, Jungwook Choi, Brian W. Curran, Bruce M. Fleischer, Kailash Gopalakrishan +3 more | 2020-11-17 |
| 10769238 | Matrix multiplication on a systolic array | Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Victor Han, Jintao Zhang | 2020-09-08 |
| 10565285 | Processor and memory transparent convolutional lowering and auto zero padding for deep neural network implementations | Jungwook Choi, Bruce M. Fleischer, Swagath Venkataramani | 2020-02-18 |
| 10528356 | Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits | Chia-Yu Chen, Kailash Gopalakrishnan, Jinwook Oh, Lee McCall Saltzman, Sunil K. Shukla | 2020-01-07 |
| 10489484 | Matrix multiplication on a systolic array | Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Victor Han, Jintao Zhang | 2019-11-26 |
| 10268588 | Methods of cache preloading on a partition or a context switch | Harold W. Cain, III, Jason D. Zebchuk | 2019-04-23 |
| 10261978 | Matrix multiplication on a systolic array | Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Victor Han, Jintao Zhang | 2019-04-16 |