Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12399743 | Padding input data for artificial intelligence accelerators | Cedric Lichtenau, Vijayalakshmi Srinivasan, Swagath Venkataramani, Kailash Gopalakrishnan, Holger Horbach +4 more | 2025-08-26 |
| 12243510 | Methods and systems for engine sound synthesis | — | 2025-03-04 |
| 12236338 | Single function to perform combined matrix multiplication and bias add operations | Cedric Lichtenau, Kailash Gopalakrishnan, Vijayalakshmi Srinivasan, Swagath Venkataramani | 2025-02-25 |
| 11941111 | Exploiting fine-grained structured weight sparsity in systolic arrays | Sanchari Sen, Swagath Venkataramani, Vijayalakshmi Srinivasan, Kailash Gopalakrishnan | 2024-03-26 |
| 11831467 | Programmable multicast protocol for ring-topology based artificial intelligence systems | Shubham Jain, Swagath Venkataramani, Vijayalakshmi Srinivasan, Martin A Lutz | 2023-11-28 |
| 11669489 | Sparse systolic array design | Swagath Venkataramani, Sanchari Sen, Vijayalakshmi Srinivasan, Ankur Agrawal, Bruce M. Fleischer +1 more | 2023-06-06 |
| 11620132 | Reusing an operand received from a first-in-first-out (FIFO) buffer according to an operand specifier value specified in a predefined field of an instruction | Bruce M. Fleischer, Vijayalakshmi Srinivasan, Jungwook Choi | 2023-04-04 |
| 11347517 | Reduced precision based programmable and SIMD dataflow architecture | Kailash Gopalakrishnan, Jungwook Choi, Silvia M. Mueller, Bruce M. Fleischer, Vijayalakshmi Srinivasan +2 more | 2022-05-31 |
| 11223703 | Instruction initialization in a dataflow architecture | Brian W. Curran, Bruce M. Fleischer, Kailash Gopalakrishnan | 2022-01-11 |
| 11216281 | Facilitating data processing using SIMD reduction operations across SIMD lanes | Bruce M. Fleischer, Kailash Gopalakrishnan, Jinwook Oh, Silvia M. Mueller | 2022-01-04 |
| 11138010 | Loop management in multi-processor dataflow architecture | Chia-Yu Chen, Jungwook Choi, Brian W. Curran, Bruce M. Fleischer, Kailash Gopalakrishnan +2 more | 2021-10-05 |
| 10838868 | Programmable data delivery by load and store agents on a processing chip interfacing with on-chip memory components and directing data to external memory components | Chia-Yu Chen, Jungwook Choi, Brian W. Curran, Bruce M. Fleischer, Kailash Gopalakrishan +3 more | 2020-11-17 |
| 10528356 | Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits | Chia-Yu Chen, Kailash Gopalakrishnan, Jinwook Oh, Lee McCall Saltzman, Vijayalakshmi Srinivasan | 2020-01-07 |
| 10216626 | Parallel garbage collection implemented in hardware | David F. Bacon, Perry S. Cheng | 2019-02-26 |
| 10120685 | Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits | Chia-Yu Chen, Kailash Gopalakrishnan, Jinwook Oh, Vijayalakshmi Srinivasan | 2018-11-06 |
| 9632928 | Parallel garbage collection implemented in hardware | David F. Bacon, Perry S. Cheng | 2017-04-25 |
| 9418187 | Cycle-accurate replay and debugging of running FPGA systems | Daniel Foisy | 2016-08-16 |
| 9355030 | Parallel garbage collection implemented in hardware | David F. Bacon, Perry S. Cheng | 2016-05-31 |
| 9329843 | Communication stack for software-hardware co-execution on heterogeneous computing systems with processors and reconfigurable logic (FPGAs) | Perry S. Cheng, Rodric Rabbah | 2016-05-03 |
| 9323506 | Communication stack for software-hardware co-execution on heterogeneous computing systems with processors and reconfigurable logic (FPGAs) | Perry S. Cheng, Rodric Rabbah | 2016-04-26 |
| 9217774 | Cycle-accurate replay and debugging of running FPGA systems | Daniel Foisy | 2015-12-22 |
| 8856491 | Garbage collection implemented in hardware | David F. Bacon, Perry S. Cheng | 2014-10-07 |
| 8566768 | Best clock frequency search for FPGA-based design | Perry S. Cheng, Rodric Rabbah | 2013-10-22 |
| 7035328 | Method of slewing a digital filter providing filter sections with matched gain | Mark W. Corless, J. William Whikehart | 2006-04-25 |
| 7027502 | Run-time coefficient generation for digital filter with slewing bandwidth | Mark W. Corless, J. William Whikehart | 2006-04-11 |