Issued Patents All Time
Showing 25 most recent of 139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411996 | Hardware-based implementation of secure hash algorithms | Manoj Kumar, Debapriya Chatterjee, Niels Fricke, Kattamuri Ekanadham, Maarten J. Boersma +1 more | 2025-09-09 |
| 12288064 | Hardware-based message block padding for hash algorithms | Manoj Kumar, Debapriya Chatterjee, Niels Fricke, Martijn Diede Berkers | 2025-04-29 |
| 11775257 | Enhanced low precision binary floating-point formatting | Ankur Agrawal, Bruce M. Fleischer, Kailash Gopalakrishnan, Dongsoo Lee | 2023-10-03 |
| 11755325 | Instruction handling for accumulation of register results in a microprocessor | Brian W. Thompto, Maarten J. Boersma, Andreas Wagner, Jose E. Moreira, Hung Q. Le +1 more | 2023-09-12 |
| 11755320 | Compute array of a processor with mixed-precision numerical linear algebra support | Jose E. Moreira, Brett Olsson, Brian W. Thompto, Andreas Wagner | 2023-09-12 |
| 11663004 | Vector convert hexadecimal floating point to scaled decimal instruction | Eric M. Schwarz, Kerstin Claudia Schelm, Petra Leber, Reid T. Copeland, Xin Guo +1 more | 2023-05-30 |
| 11620105 | Hybrid floating point representation for deep learning acceleration | Naigang Wang, Jungwook Choi, Kailash Gopalakrishnan, Ankur Agrawal | 2023-04-04 |
| 11487506 | Condition code anticipator for hexadecimal floating point | Petra Leber, Kerstin Claudia Schelm, Cedric Lichtenau | 2022-11-01 |
| 11455142 | Ultra-low precision floating-point fused multiply-accumulate unit | Ankur Agrawal, Kailash Gopalakrishnan, Bruce M. Fleischer, Balaram Sinharoy, Mingu Kang | 2022-09-27 |
| 11360769 | Decimal scale and convert and split to hexadecimal floating point instruction | Eric M. Schwarz, Petra Leber, Kerstin Claudia Schelm, Reid T. Copeland, Xin Guo +1 more | 2022-06-14 |
| 11347517 | Reduced precision based programmable and SIMD dataflow architecture | Kailash Gopalakrishnan, Sunil K. Shukla, Jungwook Choi, Bruce M. Fleischer, Vijayalakshmi Srinivasan +2 more | 2022-05-31 |
| 11314482 | Low latency floating-point division operations | Thomas W. Fox, Bruce M. Fleischer | 2022-04-26 |
| 11275561 | Mixed precision floating-point multiply-add operation | Andreas Wagner, Brian W. Thompto | 2022-03-15 |
| 11221826 | Parallel rounding for conversion from binary floating point to binary coded decimal | Stefan Payer, Razvan Peter Figuli, Revital Arieli | 2022-01-11 |
| 11216281 | Facilitating data processing using SIMD reduction operations across SIMD lanes | Bruce M. Fleischer, Kailash Gopalakrishnan, Jinwook Oh, Sunil K. Shukla | 2022-01-04 |
| 11210064 | Parallelized rounding for decimal floating point to binary coded decimal conversion | Stefan Payer, Nicol Hofmann, Razvan Peter Figuli | 2021-12-28 |
| 11188304 | Validating microprocessor performance | Gal Ashour, Oz Dov Hershkovitz, Michal Rimon, Karen Holtz, Avishai Moshe Fedida | 2021-11-30 |
| 11188328 | Compute array of a processor with mixed-precision numerical linear algebra support | Jose E. Moreira, Brett Olsson, Brian W. Thompto, Andreas Wagner | 2021-11-30 |
| 11182127 | Binary floating-point multiply and scale operation for compute-intensive numerical applications and apparatuses | Bruce M. Fleischer, Ankur Agrawal, Kailash Gopalakrishnan | 2021-11-23 |
| 11182458 | Three-dimensional lane predication for matrix operations | Brett Olsson, Brian W. Thompto, Jose E. Moreira, Andreas Wagner | 2021-11-23 |
| 11163533 | Floating point unit for exponential function implementation | Xiao Sun, Ankur Agrawal, Kailash Gopalakrishnan, Kerstin Claudia Schelm | 2021-11-02 |
| 11132228 | SMT processor to create a virtual vector register file for a borrower thread from a number of donated vector register files | Mauricio J. Serrano, Giles R. Frazier | 2021-09-28 |
| 11132198 | Instruction handling for accumulation of register results in a microprocessor | Brian W. Thompto, Maarten J. Boersma, Andreas Wagner, Jose E. Moreira, Hung Q. Le +1 more | 2021-09-28 |
| 11099853 | Digit validation check control in instruction execution | Cedric Lichtenau, Reid T. Copeland, Petra Leber, Jonathan D. Bradbury, Xin Guo | 2021-08-24 |
| 11029921 | Performing processing using hardware counters in a computer system | Eric M. Schwarz, Ulrich Mayer | 2021-06-08 |