Issued Patents All Time
Showing 1–25 of 188 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12306759 | Pseudo lock-step execution across CPU cores | Peter Hochschild | 2025-05-20 |
| 11886883 | Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction | Nicholas R. Orzol, Mehul Patel, Dung Q. Nguyen, Brian D. Barrick, Richard J. Eickemeyer +3 more | 2024-01-30 |
| 11868773 | Inferring future value for speculative branch resolution in a microprocessor | Steven J. Battle, Brian D. Barrick, Dung Q. Nguyen, Richard J. Eickemeyer, John B. Griswell, Jr. +2 more | 2024-01-09 |
| 11709676 | Inferring future value for speculative branch resolution | Steven J. Battle, Brian D. Barrick, Dung Q. Nguyen, Richard J. Eickemeyer, John B. Griswell, Jr. +2 more | 2023-07-25 |
| 11663013 | Dependency skipping execution | Nicholas R. Orzol, Mehul Patel, Dung Q. Nguyen, Brian D. Barrick, Richard J. Eickemeyer +3 more | 2023-05-30 |
| 11455142 | Ultra-low precision floating-point fused multiply-accumulate unit | Ankur Agrawal, Silvia M. Mueller, Kailash Gopalakrishnan, Bruce M. Fleischer, Mingu Kang | 2022-09-27 |
| 11256509 | Instruction fusion after register rename | Joel A. Silberman | 2022-02-22 |
| 11221770 | Providing a dynamic random-access memory cache as second type memory | Bulent Abali, Alper Buyuktosunoglu | 2022-01-11 |
| 11204772 | Coalescing global completion table entries in an out-of-order processor | Joel A. Silberman | 2021-12-21 |
| 11175925 | Load-store unit with partitioned reorder queues with single cam port | Christopher Gonzalez, Bryan Lloyd | 2021-11-16 |
| 11175924 | Load-store unit with partitioned reorder queues with single cam port | Christopher Gonzalez, Bryan Lloyd | 2021-11-16 |
| 11157280 | Dynamic fusion based on operand size | Maarten J. Boersma, Bruce M. Fleischer, Robert Alan Philhower | 2021-10-26 |
| 10977047 | Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses | Bryan Lloyd, Shih-Hsiung S. Tung | 2021-04-13 |
| 10963248 | Handling effective address synonyms in a load-store unit that operates without address translation | Bryan Lloyd | 2021-03-30 |
| 10942747 | Head and tail pointer manipulation in a first-in-first-out issue queue | Mohit Karve, Joel A. Silberman | 2021-03-09 |
| 10929140 | Scalable dependency matrix with a single summary bit in an out-of-order processor | Joel A. Silberman | 2021-02-23 |
| 10922087 | Block based allocation and deallocation of issue queue entries | Mohit Karve, Joel A. Silberman | 2021-02-16 |
| 10901744 | Buffered instruction dispatching to an issue queue | Mohit Karve, Joel A. Silberman | 2021-01-26 |
| 10884753 | Issue queue with dynamic shifting between ports | Joel A. Silberman, Brian W. Thompto | 2021-01-05 |
| 10802829 | Scalable dependency matrix with wake-up columns for long latency instructions in an out-of-order processor | Joel A. Silberman | 2020-10-13 |
| 10776113 | Executing load-store operations without address translation hardware per load-store unit port | Christopher Gonzalez, Bryan Lloyd | 2020-09-15 |
| 10713056 | Wide vector execution in single thread mode for an out-of-order processor | Silvia M. Mueller, Mauricio J. Serrano | 2020-07-14 |
| 10705847 | Wide vector execution in single thread mode for an out-of-order processor | Silvia M. Mueller, Mauricio J. Serrano | 2020-07-07 |
| 10628158 | Executing load-store operations without address translation hardware per load-store unit port | Christopher Gonzalez, Bryan Lloyd | 2020-04-21 |
| 10628166 | Allocating and deallocating reorder queue entries for an out-of-order processor | Bryan Lloyd | 2020-04-21 |