Issued Patents All Time
Showing 1–25 of 243 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12204902 | Routing instruction results to a register block of a subdivided register file based on register block utilization rate | Kurt A. Feiste, Brian W. Thompto, Susan E. Eisen, Salma Ayub | 2025-01-21 |
| 12061909 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le +1 more | 2024-08-13 |
| 11995445 | Assignment of microprocessor register tags at issue time | Steven J. Battle, Jentje Leenstra, Brian D. Barrick, Brian W. Thompto | 2024-05-28 |
| 11941398 | Fast mapper restore for flush in processor | Brian D. Barrick, Steven J. Battle, Susan E. Eisen, Cliff Kucharski, Salma Ayub | 2024-03-26 |
| 11900116 | Loosely-coupled slice target file data | Brian W. Thompto, Jose E. Moreira, Jessica Hui-Chun Tseng, Pratap C. Pattnaik, Kattamuri Ekanadham +1 more | 2024-02-13 |
| 11886883 | Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction | Nicholas R. Orzol, Mehul Patel, Brian D. Barrick, Richard J. Eickemeyer, John B. Griswell, Jr. +3 more | 2024-01-30 |
| 11868773 | Inferring future value for speculative branch resolution in a microprocessor | Steven J. Battle, Brian D. Barrick, Richard J. Eickemeyer, John B. Griswell, Jr., Balaram Sinharoy +2 more | 2024-01-09 |
| 11768684 | Compaction of architected registers in a simultaneous multithreading processor | Steven J. Battle, Albert J. Van Norstrand, Jr., Tu-An T. Nguyen, Cliff Kucharski | 2023-09-26 |
| 11755325 | Instruction handling for accumulation of register results in a microprocessor | Brian W. Thompto, Maarten J. Boersma, Andreas Wagner, Jose E. Moreira, Hung Q. Le +1 more | 2023-09-12 |
| 11748104 | Microprocessor that fuses load and compare instructions | Bryan Lloyd, David A. Hrusecky, Sundeep Chadha, Christian Zoellin, Brian W. Thompto +2 more | 2023-09-05 |
| 11734010 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le +1 more | 2023-08-22 |
| 11709676 | Inferring future value for speculative branch resolution | Steven J. Battle, Brian D. Barrick, Richard J. Eickemeyer, John B. Griswell, Jr., Balaram Sinharoy +2 more | 2023-07-25 |
| 11663013 | Dependency skipping execution | Nicholas R. Orzol, Mehul Patel, Brian D. Barrick, Richard J. Eickemeyer, John B. Griswell, Jr. +3 more | 2023-05-30 |
| 11635961 | Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file | Christopher M. Abernathy, Mary D. Brown | 2023-04-25 |
| 11561794 | Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry | Steven J. Battle, Brian W. Thompto, Cliff Kucharski, Susan E. Eisen, Salma Ayub | 2023-01-24 |
| 11561798 | On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer | Brian D. Barrick, Maarten J. Boersma, Niels Fricke, Brian W. Thompto, Andreas Wagner | 2023-01-24 |
| 11537402 | Execution elision of intermediate instruction by processor | Brian D. Barrick, Bryan Lloyd, Brian W. Thompto, Edmund J. Gieske, John B. Griswell, Jr. | 2022-12-27 |
| 11531548 | Fast perfect issue of dependent instructions in a distributed issue queue system | Brian D. Barrick, Brian W. Thompto, Tu-An T. Nguyen, Salma Ayub | 2022-12-20 |
| 11500642 | Assignment of microprocessor register tags at issue time | Steven J. Battle, Jentje Leenstra, Brian D. Barrick, Brian W. Thompto | 2022-11-15 |
| 11403109 | Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor | Steven J. Battle, Khandker N. Adeeb, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen +2 more | 2022-08-02 |
| 11392386 | Program counter (PC)-relative load and store addressing for fused instructions | Nicholas R. Orzol, Christian Zoellin, Brian W. Thompto, Niels Fricke, Sheldon B. Levenstein +2 more | 2022-07-19 |
| 11366671 | Completion mechanism for a microprocessor instruction completion table | Kenneth L. Ward, Susan E. Eisen, Glenn O. Kincaid, Joe Lee, Deepak Singh | 2022-06-21 |
| 11360779 | Logical register recovery within a processor | Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen +2 more | 2022-06-14 |
| 11360775 | Slice-based allocation history buffer | Brian D. Barrick, Gregory W. Alexander | 2022-06-14 |
| 11327766 | Instruction dispatch routing | Eric M. Schwarz, Brian W. Thompto, Kurt A. Feiste, Michael J. Genden, Susan E. Eisen | 2022-05-10 |