Issued Patents All Time
Showing 1–25 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411996 | Hardware-based implementation of secure hash algorithms | Manoj Kumar, Silvia M. Mueller, Debapriya Chatterjee, Niels Fricke, Kattamuri Ekanadham +1 more | 2025-09-09 |
| 11755325 | Instruction handling for accumulation of register results in a microprocessor | Brian W. Thompto, Andreas Wagner, Jose E. Moreira, Hung Q. Le, Silvia M. Mueller +1 more | 2023-09-12 |
| 11561798 | On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer | Brian D. Barrick, Niels Fricke, Dung Q. Nguyen, Brian W. Thompto, Andreas Wagner | 2023-01-24 |
| 11182167 | Method to determine the oldest instruction in an instruction queue of a processor with multiple instruction threads | Arni Ingimundarson, Niels Fricke | 2021-11-23 |
| 11157276 | Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entry | Steven J. Battle, Niels Fricke, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto | 2021-10-26 |
| 11157280 | Dynamic fusion based on operand size | Bruce M. Fleischer, Robert Alan Philhower, Balaram Sinharoy | 2021-10-26 |
| 11132198 | Instruction handling for accumulation of register results in a microprocessor | Brian W. Thompto, Andreas Wagner, Jose E. Moreira, Hung Q. Le, Silvia M. Mueller +1 more | 2021-09-28 |
| 11093246 | Banked slice-target register file for wide dataflow execution in a microprocessor | Niels Fricke, Michael K. Kroener, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto | 2021-08-17 |
| 10996953 | Low latency execution of floating-point record form instructions | Brian J. D. Barrick, Niels Fricke, Michael J. Genden | 2021-05-04 |
| 10831496 | Method to execute successive dependent instructions from an instruction stream in a processor | Michael K. Kroener, Niels Fricke, Razvan Peter Figuli, Nandor Szirmak, Dung Q. Nguyen | 2020-11-10 |
| 10768897 | Arithmetic logic unit for single-cycle fusion operations | Niels Fricke | 2020-09-08 |
| 10678547 | Low latency execution of floating-point record form instructions | Brian J. D. Barrick, Niels Fricke, Michael J. Genden | 2020-06-09 |
| 10671398 | Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core | Sundeep Chadha, Kurt A. Feiste, Michael J. Genden, Michael K. Kroener, David R. Terry | 2020-06-02 |
| 10671399 | Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core | Sundeep Chadha, Kurt A. Feiste, Michael J. Genden, Michael K. Kroener, David R. Terry | 2020-06-02 |
| 10592246 | Low latency execution of floating-point record form instructions | Brian J. D. Barrick, Niels Fricke, Michael J. Genden | 2020-03-17 |
| 10545727 | Arithmetic logic unit for single-cycle fusion operations | Niels Fricke | 2020-01-28 |
| 10360036 | Cracked execution of move-to-FPSCR instructions | Brian J. D. Barrick, Niels Fricke, Michael J. Genden | 2019-07-23 |
| 10223196 | ECC scrubbing method in a multi-slice microprocessor | Brian D. Barrick, James Wilson Bishop, Marcy E. Byers, Sundeep Chadha, Jentje Leenstra +2 more | 2019-03-05 |
| 10169046 | Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction | Robert A. Cordes, David A. Hrusecky, Jennifer L. Molnar, Brian W. Thompto, Albert J. Van Norstrand, Jr. +1 more | 2019-01-01 |
| 9846614 | ECC scrubbing in a multi-slice microprocessor | Brian D. Barrick, James Wilson Bishop, Marcy E. Byers, Sundeep Chadha, Jentje Leenstra +2 more | 2017-12-19 |
| 9798549 | Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction | Robert A. Cordes, David A. Hrusecky, Jennifer L. Molnar, Brian W. Thompto, Albert J. Van Norstrand, Jr. +1 more | 2017-10-24 |
| 9760375 | Register files for storing data operated on by instructions of multiple widths | Markus Kaltenbach, David Lang, Jentje Leenstra | 2017-09-12 |
| 9753690 | Splitable and scalable normalizer for vector data | Markus Kaltenbach, Christophe J. Layer, Silvia M. Mueller | 2017-09-05 |
| 9740486 | Register files for storing data operated on by instructions of multiple widths | Markus Kaltenbach, David Lang, Jentje Leenstra | 2017-08-22 |
| 9361267 | Splitable and scalable normalizer for vector data | Markus Kaltenbach, Christophe J. Layer, Silvia M. Mueller | 2016-06-07 |