Issued Patents All Time
Showing 1–25 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411688 | Gather buffer management for unaligned and gather load operations | Kimberly M. Fernsler, Bryan Lloyd, David Campbell | 2025-09-09 |
| 12061909 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Sundeep Chadha, Robert A. Cordes, Hung Q. Le, Dung Q. Nguyen +1 more | 2024-08-13 |
| 11755324 | Gather buffer management for unaligned and gather load operations | Kimberly M. Fernsler, Bryan Lloyd, David Campbell | 2023-09-12 |
| 11748104 | Microprocessor that fuses load and compare instructions | Bryan Lloyd, Sundeep Chadha, Dung Q. Nguyen, Christian Zoellin, Brian W. Thompto +2 more | 2023-09-05 |
| 11734010 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Sundeep Chadha, Robert A. Cordes, Hung Q. Le, Dung Q. Nguyen +1 more | 2023-08-22 |
| 11379241 | Handling oversize store to load forwarding in a processor | Bryan Lloyd, Brian Chen, Kimberly M. Fernsler, Robert A. Cordes | 2022-07-05 |
| 11321088 | Tracking load and store instructions and addresses in an out-of-order processor | Bryan Lloyd, Samuel David Kirchhoff, Brian Chen, Kimberly M. Fernsler | 2022-05-03 |
| 11314510 | Tracking load and store instructions and addresses in an out-of-order processor | Bryan Lloyd, Samuel David Kirchhoff, Brian Chen, Kimberly M. Fernsler | 2022-04-26 |
| 11263151 | Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations | David Campbell, Bryan Lloyd, Kimberly M. Fernsler, Jeffrey A. Stuecheli, Guy L. Guthrie +4 more | 2022-03-01 |
| 11150907 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Sundeep Chadha, Robert A. Cordes, Hung Q. Le, Dung Q. Nguyen +1 more | 2021-10-19 |
| 11061810 | Virtual cache mechanism for program break point register exception handling | David Campbell, Dwain A. Hicks, Bryan Lloyd | 2021-07-13 |
| 10884742 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more | 2021-01-05 |
| 10831481 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more | 2020-11-10 |
| 10761854 | Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor | Robert A. Cordes, Elizabeth A. McGlone | 2020-09-01 |
| 10606600 | Fetched data in an ultra-short piped load store unit | — | 2020-03-31 |
| 10564978 | Operation of a multi-slice processor with an expanded merge fetching queue | Kimberly M. Fernsler, Hung Q. Le, Elizabeth A. McGlone, Brian W. Thompto | 2020-02-18 |
| 10552165 | Efficiently managing speculative finish tracking and error handling for load instructions | Susan E. Eisen, Christopher M. Mueller, Dung Q. Nguyen, A. James Van Norstrand, Jr., Kenneth L. Ward | 2020-02-04 |
| 10496406 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more | 2019-12-03 |
| 10423423 | Efficiently managing speculative finish tracking and error handling for load instructions | Susan E. Eisen, Christopher M. Mueller, Dung Q. Nguyen, A. James Van Norstrand, Jr., Kenneth L. Ward | 2019-09-24 |
| 10409598 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more | 2019-09-10 |
| 10318419 | Flush avoidance in a load store unit | Sundeep Chadha, Elizabeth A. McGlone, George W. Rohrbaugh, III, Shih-Hsiung S. Tung | 2019-06-11 |
| 10268518 | Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions | Sundeep Chadha, Robert A. Cordes, Hung Q. Le, Elizabeth A. McGlone | 2019-04-23 |
| 10255107 | Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions | Sundeep Chadha, Robert A. Cordes, Hung Q. Le, Elizabeth A. McGlone | 2019-04-09 |
| 10169046 | Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction | Maarten J. Boersma, Robert A. Cordes, Jennifer L. Molnar, Brian W. Thompto, Albert J. Van Norstrand, Jr. +1 more | 2019-01-01 |
| 10133576 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Sundeep Chadha, Robert A. Cordes, Hung Q. Le, Dung Q. Nguyen +1 more | 2018-11-20 |