ST

Shih-Hsiung S. Tung

IBM: 32 patents #3,111 of 70,183Top 5%
🗺 Texas: #3,516 of 125,132 inventorsTop 3%
Overall (All Time): #112,852 of 4,157,543Top 3%
32
Patents All Time

Issued Patents All Time

Showing 1–25 of 32 patents

Patent #TitleCo-InventorsDate
11157415 Operation of a multi-slice processor implementing a unified page walk cache Dwain A. Hicks, Jonathan H. Raymond, George W. Rohrbaugh, III 2021-10-26
10977047 Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses Bryan Lloyd, Balaram Sinharoy 2021-04-13
10824494 Operation of a multi-slice processor implementing exception handling in a nested translation environment Dwain A. Hicks, Jonathan H. Raymond 2020-11-03
10664275 Speeding up younger store instruction execution after a sync instruction Susan E. Eisen, Hung Q. Le, Bryan Lloyd, Dung Q. Nguyen, David Scott Ray +1 more 2020-05-26
10534715 Operation of a multi-slice processor implementing a unified page walk cache Dwain A. Hicks, Jonathan H. Raymond, George W. Rohrbaugh, III 2020-01-14
10417002 Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses Bryan Lloyd, Balaram Sinharoy 2019-09-17
10324856 Address translation for sending real address to memory subsystem in effective address based load-store unit Bryan Lloyd, Balaram Sinharoy 2019-06-18
10318419 Flush avoidance in a load store unit Sundeep Chadha, David A. Hrusecky, Elizabeth A. McGlone, George W. Rohrbaugh, III 2019-06-11
10310988 Address translation for sending real address to memory subsystem in effective address based load-store unit Bryan Lloyd, Balaram Sinharoy 2019-06-04
10067765 Speeding up younger store instruction execution after a sync instruction Susan E. Eisen, Hung Q. Le, Bryan Lloyd, Dung Q. Nguyen, David Scott Ray +1 more 2018-09-04
10042691 Operation of a multi-slice processor implementing exception handling in a nested translation environment Dwain A. Hicks, Jonathan H. Raymond 2018-08-07
9086987 Detection of conflicts between transactions and page shootdowns Harold W. Cain, III, Hung Q. Le, Bryan Lloyd 2015-07-21
9086986 Detection of conflicts between transactions and page shootdowns Harold W. Cain, III, Hung Q. Le, Bryan Lloyd 2015-07-21
8086801 Loading data to vector renamed register from across multiple cache lines David A. Hrusecky, David Scott Ray, Bruce Joseph Ronchetti 2011-12-27
7949859 Mechanism for avoiding check stops in speculative accesses while operating in real mode Ronald Nick Kalla, Cathy May, Balaram Sinharoy, Edward John Silha 2011-05-24
7370177 Mechanism for avoiding check stops in speculative accesses while operating in real mode Ronald Nick Kalla, Cathy May, Balaram Sinharoy, Edward John Silha 2008-05-06
7254678 Enhanced STCX design to improve subsequent load efficiency Gregory W. Alexander, Juan Jose Arevalo, Balaram Sinharoy 2007-08-07
6463514 Method to arbitrate for a cache block David Scott Ray, Pei-Chun Liu 2002-10-08
6446170 Efficient store machine in cache based microprocessor Kin Shing Chan, Dwain A. Hicks, Michael John Mayfield 2002-09-03
6430680 Processor and method of prefetching data based upon a detected stride William E. Burky, David A. Schroter, Michael Thomas Vaden 2002-08-06
6304939 Token mechanism for cache-line replacement within a cache memory having redundant cache lines Peichun Peter Liu, Rajinder Paul Singh 2001-10-16
6298417 Pipelined cache memory deallocation and storeback Kin Shing Chan, Dwain A. Hicks, Michael John Mayfield 2001-10-02
6275918 Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold William E. Burky, Peter Steven Lenk, Dung Q. Nguyen, David A. Schroter, Michael Thomas Vaden 2001-08-14
6240487 Integrated cache buffers Pei-Chun Liu, Rajinder Paul Singh, Dwain A. Hicks, Kin Shing Chan 2001-05-29
6202128 Method and system for pre-fetch cache interrogation using snoop port Kin Shing Chan, Dwain A. Hicks, Peichun Peter Liu, Michael John Mayfield 2001-03-13