Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10261791 | Bypassing memory access for a load instruction using instruction address mapping | Brian R. Prasky, Chung-Lung K. Shum, Corey C Stappenbeck | 2019-04-16 |
| 10108426 | Dynamic issue masks for processor hang prevention | Gregory W. Alexander, Steven R. Carlough, Lee Evan Eisen | 2018-10-23 |
| 10102002 | Dynamic issue masks for processor hang prevention | Gregory W. Alexander, Steven R. Carlough, Lee Evan Eisen | 2018-10-16 |
| 9880847 | Register file mapping | Gregory W. Alexander, Brian D. Barrick, Lee Evan Eisen | 2018-01-30 |
| 9104399 | Dual issuing of complex instruction set instructions | Fadi Y. Busaba, Brian W. Curran, Lee Evan Eisen, Christian Jacobi, Eric M. Schwarz | 2015-08-11 |
| 9075600 | Program status word dependency handling in an out of order microprocessor design | Gregory W. Alexander, Brian D. Barrick, Michael Billeci, Fadi Y. Busaba, Bruce C. Giamei | 2015-07-07 |
| 8549255 | Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system | Mark S. Farrell, Jennifer Serena Almoradie Navarro, Chung-Lung K. Shum, Charles F. Webb | 2013-10-01 |
| 8082467 | Triggering workaround capabilities based on events active in a processor pipeline | Gregory W. Alexander, Fadi Y. Busaba, Eric M. Schwarz, Brian W. Thompto, Wesley J. Ward, III | 2011-12-20 |
| 7966474 | System, method and computer program product for translating storage elements | Chung-Lung K. Shum, Fadi Y. Busaba, Mark S. Farrell, Bruce C. Giamei, Bernd Nerz +1 more | 2011-06-21 |
| 7363625 | Method for changing a thread priority in a simultaneous multithread processor | William E. Burky, Ronald Nick Kalla, Balaram Sinharoy | 2008-04-22 |
| 7290261 | Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor | William E. Burky, Bjorn P. Christensen, Dung Q. Nguyen, Albert Thomas Williams | 2007-10-30 |
| 7194603 | SMT flush arbitration | William E. Burky, Hung Q. Le, Dung Q. Nguyen | 2007-03-20 |
| 7089406 | Method and apparatus for controlling program instruction completion timing for processor verification | John Martin Ludden, Darin M. Greene, Wallace Sharp | 2006-08-08 |
| 6792524 | System and method cancelling a speculative branch | Milford John Peterson, Albert J. Van Norstrand, Jr. | 2004-09-14 |
| 6430680 | Processor and method of prefetching data based upon a detected stride | William E. Burky, Shih-Hsiung S. Tung, Michael Thomas Vaden | 2002-08-06 |
| 6401192 | Apparatus for software initiated prefetch and method therefor | Michael Thomas Vaden | 2002-06-04 |
| 6338133 | Measured, allocation of speculative branch instructions to processor execution units | — | 2002-01-08 |
| 6275918 | Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold | William E. Burky, Peter Steven Lenk, Dung Q. Nguyen, Shih-Hsiung S. Tung, Michael Thomas Vaden | 2001-08-14 |
| 6061785 | Data processing system having an apparatus for out-of-order register operations and method therefor | Kevin Arthur Chiarot, A. James Van Norstrand, Jr. | 2000-05-09 |
| 6035394 | System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel | David Scott Ray, Kevin Arthur Chiarot, A. James Van Norstrand, Jr., Barry Duane Williamson | 2000-03-07 |
| 5953510 | Bidirectional data bus reservation priority controls having token logic | Robert D. Herzl | 1999-09-14 |
| 5850542 | Microprocessor instruction hedge-fetching in a multiprediction branch environment | A. James Van Norstrand, Jr. | 1998-12-15 |
| 5835714 | Method and apparatus for reservation of data buses between multiple storage control elements | Robert D. Herzl | 1998-11-10 |
| 5764970 | Method and apparatus for supporting speculative branch and link/branch on count instructions | Deepak Rana | 1998-06-09 |
| 5416911 | Performance enhancement for load multiple register instruction | Robert M. Dinkjian, Fredrick W. Roberts | 1995-05-16 |