Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10372618 | Apparatus and method for maintaining address translation data within an address translation cache | Miles Robert Dooley, Abhishek Raja, Huzefa Sanjeliwala | 2019-08-06 |
| 10102143 | Eviction control for an address translation cache | Michael Filippo, Abhishek Raja, Adrian Montero, Miles Robert Dooley | 2018-10-16 |
| 8271733 | Line allocation in multi-level hierarchical data stores | — | 2012-09-18 |
| 7900020 | Correction of incorrect cache accesses | Gerard R. Williams, III, Muralidharan S. Chinnakonda | 2011-03-01 |
| 6532574 | Post-manufacture signal delay adjustment to solve noise-induced delay variations | Christopher McCall Durham, Sharad Mehrotra, Alexander K. Spencer | 2003-03-11 |
| 6405352 | Method and system for analyzing wire-only changes to a microprocessor design using delta model | Alexander K. Spencer | 2002-06-11 |
| 6192461 | Method and apparatus for facilitating multiple storage instruction completions in a superscalar processor during a single clock cycle | Jim Phillips, Dq Nguyen | 2001-02-20 |
| 6148394 | Apparatus and method for tracking out of order load instructions to avoid data coherency violations in a processor | Shih-Hsiung S. Tung, David Scott Ray, Kevin Arthur Chiarot | 2000-11-14 |
| 6112297 | Apparatus and method for processing misaligned load instructions in a processor supporting out of order execution | David Scott Ray, Shih-Hsiung S. Tung | 2000-08-29 |
| 6035394 | System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel | David Scott Ray, Kevin Arthur Chiarot, David A. Schroter, A. James Van Norstrand, Jr. | 2000-03-07 |
| 5926645 | Method and system for enabling multiple store instruction completions in a processing system | — | 1999-07-20 |