Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423111 | Static instruction caching in a coprocessor architecture | — | 2025-09-23 |
| 12182427 | Controlling data allocation to storage circuitry | Stefano GHIGGINI, Natalya Bondarenko, Luca NASSI, Geoffray Matthieu Lacourba, Huzefa Sanjeliwala +1 more | 2024-12-31 |
| 12067395 | Pre-staged instruction registers for variable length instruction set machine | Milos Trajkovic, Rakesh Shaji Lal, Stanislav Sokorac | 2024-08-20 |
| 11599358 | Pre-staged instruction registers for variable length instruction set machine | Milos Trajkovic, Rakesh Shaji Lal, Stanislav Sokorac | 2023-03-07 |
| 11543994 | Controlling access requests of request nodes | Ho-Seop Kim, Joseph Michael Pusdesris | 2023-01-03 |
| 11263138 | Correlated addresses and prefetching | Joseph Michael Pusdesris, Michael Filippo | 2022-03-01 |
| 11194574 | Merging memory ordering tracking information for issued load instructions | Balaji Vijayan, Huzefa Sanjeliwala, Abhishek Raja, Sharmila Shridhar | 2021-12-07 |
| 10983916 | Cache storage | Huzefa Sanjeliwala, Klas Magnus Bruce, Leigang Kou, Michael Filippo, Matthew A. Rafacz | 2021-04-20 |
| 10776043 | Storage circuitry request tracking | Adrian Montero, Joseph Michael Pusdesris, Klas Magnus Bruce, Chris Abernathy | 2020-09-15 |
| 10769070 | Multiple stride prefetching | Joseph Michael Pusdesris, Alexander Cole Shulyak, Krishnendra Nathella, Dam Sunwoo | 2020-09-08 |
| 10528480 | Apparatus and method for efficient utilisation of an address translation cache | Rakesh Shaji Lal | 2020-01-07 |
| 10372618 | Apparatus and method for maintaining address translation data within an address translation cache | Abhishek Raja, Barry Duane Williamson, Huzefa Sanjeliwala | 2019-08-06 |
| 10229066 | Queuing memory access requests | Matthew A. Rafacz, Huzefa Sanjeliwala, Michael Filippo | 2019-03-12 |
| 10102143 | Eviction control for an address translation cache | Barry Duane Williamson, Michael Filippo, Abhishek Raja, Adrian Montero | 2018-10-16 |
| 9864694 | Tracking the content of a cache using a way tracker having entries with a cache miss indicator | Todd Rafacz, Guy Larri | 2018-01-09 |
| 9495297 | Cache line crossing load techniques for a caching system | David A. Hrusecky | 2016-11-15 |
| 9495298 | Cache line crossing load techniques | David A. Hrusecky | 2016-11-15 |
| 9465744 | Data prefetch ramp implemenation based on memory utilization | Jason N. Dale, Richard J. Eickemeyer, John B. Griswell, Jr., Francis Patrick O'Connell, Jeffrey A. Stuecheli | 2016-10-11 |
| 9384136 | Modification of prefetch depth based on high latency event | John Steven Dodson, Benjiman L. Goodman, Jody B. Joyner, Stephen J. Powell, Eric E. Retter +1 more | 2016-07-05 |
| 9378144 | Modification of prefetch depth based on high latency event | John Steven Dodson, Benjiman L. Goodman, Jody B. Joyner, Stephen J. Powell, Eric E. Retter +1 more | 2016-06-28 |
| 8949579 | Ineffective prefetch determination and latency optimization | Venkat R. Indukuru, Alex E. Mericas, Francis Patrick O'Connell | 2015-02-03 |
| 8862859 | Efficient support of multiple page size segments | Sundeep Chadha, Naresh Nayar, Randal C. Swanberg | 2014-10-14 |
| 8856453 | Persistent prefetch data stream settings | Jason N. Dale, Richard J. Eickemeyer, Bradly G. Frey, Yaoqing Gao, Francis Patrick O'Connell +1 more | 2014-10-07 |
| 8549235 | Method for detecting address match in a deeply pipelined processor design | Scott Bruce Frommer, David A. Hrusecky, Sheldon B. Levenstein | 2013-10-01 |
| 8156287 | Adaptive data prefetch | Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd, David Scott Ray, Bruce Joseph Ronchetti | 2012-04-10 |