Issued Patents All Time
Showing 25 most recent of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11734188 | Unified translation miss queue for multiple address translation modes | Charles D. Wait, David Campbell, Jake Truelove, Jon K. Kriegel, Glenn O. Kincaid | 2023-08-22 |
| 11636043 | Sleeping and waking-up address translation that conflicts with translation level of active page table walks | Charles D. Wait, Jake Truelove, David Campbell, Jon K. Kriegel, Glenn O. Kincaid | 2023-04-25 |
| 11556475 | Power optimized prefetching in set-associative translation lookaside buffer structure | David Campbell, George W. Rohrbaugh, III, Jake Truelove, Jon K. Kriegel, Charles D. Wait | 2023-01-17 |
| 11221957 | Promotion of ERAT cache entries | Bartholomew Blaner, Jay G. Heaslip, Benjamin Herrenschmidt, Robert D. Herzl, Jon K. Kriegel +1 more | 2022-01-11 |
| 10884943 | Speculative checkin of ERAT cache entries | Bartholomew Blaner, Jay G. Heaslip, Robert D. Herzl, Jeffrey A. Stuecheli | 2021-01-05 |
| 10776281 | Snoop invalidate filter for distributed memory management unit to reduce snoop invalidate latency | Jake Truelove, Ronald Nick Kalla, Benjamin Herrenschmidt, David A. Larson Stanton | 2020-09-15 |
| 10671537 | Reducing translation latency within a memory management unit using external caching structures | Guy L. Guthrie, Ronald Nick Kalla, Michael S. Siegel, Jeffrey A. Stuecheli, Charles D. Wait +1 more | 2020-06-02 |
| 10649902 | Reducing translation latency within a memory management unit using external caching structures | Guy L. Guthrie, Ronald Nick Kalla, Michael S. Siegel, Jeffrey A. Stuecheli, Charles D. Wait +1 more | 2020-05-12 |
| 10599569 | Maintaining consistency between address translations in a data processing system | Bartholomew Blaner, Jay G. Heaslip, Robert D. Herzl | 2020-03-24 |
| 10380031 | Ensuring forward progress for nested translations in a memory management unit | Guy L. Guthrie, Jon K. Kriegel, Bradley Nelson, Charles D. Wait | 2019-08-13 |
| 10318435 | Ensuring forward progress for nested translations in a memory management unit | Guy L. Guthrie, Jon K. Kriegel, Bradley Nelson, Charles D. Wait | 2019-06-11 |
| 9384136 | Modification of prefetch depth based on high latency event | John Steven Dodson, Miles Robert Dooley, Benjiman L. Goodman, Stephen J. Powell, Eric E. Retter +1 more | 2016-07-05 |
| 9378144 | Modification of prefetch depth based on high latency event | John Steven Dodson, Miles Robert Dooley, Benjiman L. Goodman, Stephen J. Powell, Eric E. Retter +1 more | 2016-06-28 |
| 9355035 | Dynamic write priority based on virtual write queue high water mark for set associative cache using cache cleaner when modified sets exceed threshold | Benjiman L. Goodman, Stephen J. Powell, William J. Starke, Jeffrey A. Stuecheli | 2016-05-31 |
| 9336145 | Techniques for cache injection in a processor system based on a shared state | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, William J. Starke | 2016-05-10 |
| 9268703 | Techniques for cache injection in a processor system from a remote node | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, William J. Starke | 2016-02-23 |
| 9218292 | Least-recently-used (LRU) to first-dirty-member distance-maintaining cache cleaning scheduler | Benjiman L. Goodman, Stephen J. Powell, Aaron C. Sawdey, Jeffrey A. Stuecheli | 2015-12-22 |
| 9213647 | Least-recently-used (LRU) to first-dirty-member distance-maintaining cache cleaning scheduler | Benjiman L. Goodman, Stephen J. Powell, Aaron C. Sawdey, Jeffrey A. Stuecheli | 2015-12-15 |
| 8417778 | Collective acceleration unit tree flow control and retransmit | Lakshminarayana B. Arimilli, Bernard C. Drerup, Paul Frank Lecocq, Hanhong Xue | 2013-04-09 |
| 8302109 | Synchronization optimized queuing system | Lakshminarayana B. Arimilli, Claude Basso, Piyush Chaudhary, Bernard C. Drerup, Jan-Bernd Themann +2 more | 2012-10-30 |
| 8077602 | Performing dynamic request routing based on broadcast queue depths | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Bernard C. Drerup, Jerry Don Lewis | 2011-12-13 |
| 7921316 | Cluster-wide system clock in a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Bernard C. Drerup, Jerry Don Lewis | 2011-04-05 |
| 7827428 | System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Bernard C. Drerup, Jerry Don Lewis | 2010-11-02 |
| 7779148 | Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Bernard C. Drerup, Jerry Don Lewis | 2010-08-17 |
| 7526631 | Data processing system with backplane and processor books configurable to support both technical and commercial workloads | Ravi Kumar Arimilli, Vicente Enrique Chung, Jerry Don Lewis | 2009-04-28 |