Issued Patents All Time
Showing 25 most recent of 238 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10949346 | Data flush of a persistent memory cache or buffer | Derek E. Williams, Guy L. Guthrie | 2021-03-16 |
| 10176125 | Dynamically adjusting read data return sizes based on interconnect bus utilization | Didier Louis, Eric E. Retter, Jeffrey A. Stuecheli | 2019-01-08 |
| 10019370 | Probabilistic associative cache | Bulent Abali, Moinuddin K. Qureshi, Balaram Sinharoy | 2018-07-10 |
| 9892066 | Dynamically adjusting read data return sizes based on interconnect bus utilization | Didier Louis, Eric E. Retter, Jeffrey A. Stuecheli | 2018-02-13 |
| 9684461 | Dynamically adjusting read data return sizes based on memory interface bus utilization | Stephen J. Powell, Eric E. Retter, Jeffrey A. Stuecheli | 2017-06-20 |
| 9632954 | Memory queue handling techniques for reducing impact of high-latency memory operations | Mark A. Brittain, Benjiman L. Goodman, Stephen J. Powell, Eric E. Retter, Jeffrey A. Stuecheli | 2017-04-25 |
| 9594646 | Reestablishing synchronization in a memory system | Glenn D. Gilda, Patrick J. Meaney, Vesselina K. Papazova | 2017-03-14 |
| 9594647 | Synchronization and order detection in a memory system | Patrick J. Meaney, Glenn D. Gilda, Eric E. Retter, Gary A. Van Huben, Brad W. Michael +1 more | 2017-03-14 |
| 9568986 | System-wide power conservation using memory cache | Malcolm S. Allen-Ware, Jordan R. Keuseman, Karthick Rajamani, Srinivasan Ramani, Todd J. Rosedahl +2 more | 2017-02-14 |
| 9535778 | Reestablishing synchronization in a memory system | Glenn D. Gilda, Patrick J. Meaney, Vesselina K. Papazova | 2017-01-03 |
| 9495254 | Synchronization and order detection in a memory system | Patrick J. Meaney, Glenn D. Gilda, Eric E. Retter, Gary A. Van Huben, Brad W. Michael +1 more | 2016-11-15 |
| 9495231 | Reestablishing synchronization in a memory system | Glenn D. Gilda, Patrick J. Meaney, Vesselina K. Papazova | 2016-11-15 |
| 9471410 | Transient condition management utilizing a posted error detection processing protocol | Benjiman L. Goodman, Guy L. Guthrie, Eric E. Retter, William J. Starke, Jeffrey A. Stuecheli | 2016-10-18 |
| 9430418 | Synchronization and order detection in a memory system | Patrick J. Meaney, Glenn D. Gilda, Eric E. Retter, Gary A. Van Huben, Brad W. Michael +1 more | 2016-08-30 |
| 9424194 | Probabilistic associative cache | Bulent Abali, Moinuddin K. Qureshi, Balaram Sinharoy | 2016-08-23 |
| 9384136 | Modification of prefetch depth based on high latency event | Miles Robert Dooley, Benjiman L. Goodman, Jody B. Joyner, Stephen J. Powell, Eric E. Retter +1 more | 2016-07-05 |
| 9378144 | Modification of prefetch depth based on high latency event | Miles Robert Dooley, Benjiman L. Goodman, Jody B. Joyner, Stephen J. Powell, Eric E. Retter +1 more | 2016-06-28 |
| 9128834 | Implementing memory module communications with a host processor in multiported memory configurations | Luis A. Lastras-Montano, Warren E. Maule, Adam J. McPadden, Kenneth L. Wright | 2015-09-08 |
| 9086997 | Memory uncorrectable error handling technique for reducing the impact of noise | Benjiman L. Goodman, Stephen J. Powell, Kenneth L. Wright | 2015-07-21 |
| 9086998 | Memory uncorrectable error handling technique for reducing the impact of noise | Benjiman L. Goodman, Stephen J. Powell, Kenneth L. Wright | 2015-07-21 |
| 9058260 | Transient condition management utilizing a posted error detection processing protocol | Benjiman L. Goodman, Guy L. Guthrie, Eric E. Retter, William J. Starke, Jeffrey A. Stuecheli | 2015-06-16 |
| 9058178 | Selective posted data error detection based on request type | Robert Alan Cargnoni, Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli | 2015-06-16 |
| 8996824 | Memory reorder queue biasing preceding high latency operations | Mark A. Brittain, Stephen J. Powell, Eric E. Retter, Jeffrey A. Stuecheli | 2015-03-31 |
| 8990640 | Selective posted data error detection based on request type | Robert Alan Cargnoni, Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli | 2015-03-24 |
| 8909874 | Memory reorder queue biasing preceding high latency operations | Mark A. Brittain, Stephen J. Powell, Eric E. Retter, Jeffrey A. Stuecheli | 2014-12-09 |