Issued Patents All Time
Showing 25 most recent of 138 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12380004 | Dynamic multi-lane degrade capability to facilitate uninterrupted service | Rajat Rao, Ashutosh Mishra, Jason Andrew Thompson, Nandini Gaadam Nagaraj | 2025-08-05 |
| 12188979 | Error protection analysis of an integrated circuit | Benjamin Neil Trombley, Chung-Lung K. Shum, Karl Evan Smock Anderson, Bodo Hoppe, Erica Stuecheli +3 more | 2025-01-07 |
| 11960426 | Cable pair concurrent servicing | Rajat Rao, Glenn D. Gilda, Michael Jason Cade, Robert J. Sonnelitter, III, Hubert Harrer +3 more | 2024-04-16 |
| 11907074 | Low-latency deserializer having fine granularity and defective-lane compensation | Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan I. Friedman, Jentje Leenstra +2 more | 2024-02-20 |
| 11687254 | Host synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Susan M. Eickhoff, Stephen J. Powell, Gary A. Van Huben, Jie Zheng | 2023-06-27 |
| 11646861 | Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes | Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan I. Friedman, Jentje Leenstra +3 more | 2023-05-09 |
| 11609817 | Low latency availability in degraded redundant array of independent memory | Glenn D. Gilda, David D. Cadigan, Lawrence W. Jones | 2023-03-21 |
| 11587600 | Address/command chip controlled data chip address sequencing for a distributed memory buffer system | Steven R. Carlough, Susan M. Eickhoff, Warren E. Maule, Stephen J. Powell, Gary A. Van Huben +1 more | 2023-02-21 |
| 11520659 | Refresh-hiding memory system staggered refresh | Glenn D. Gilda, David D. Cadigan, Christian Jacobi, Lawrence W. Jones, Stephen J. Powell | 2022-12-06 |
| 11379123 | Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Susan M. Eickhoff, Stephen J. Powell, Gary A. Van Huben, Jie Zheng | 2022-07-05 |
| 11200119 | Low latency availability in degraded redundant array of independent memory | Glenn D. Gilda, David D. Cadigan, Lawrence W. Jones | 2021-12-14 |
| 11088782 | Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection | Steven R. Carlough, Gary A. Van Huben | 2021-08-10 |
| 10976939 | Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Susan M. Eickhoff, Stephen J. Powell, Gary A. Van Huben, Jie Zheng | 2021-04-13 |
| 10901839 | Common high and low random bit error correction logic | James A. O'Connor, Barry M. Trager, Warren E. Maule, Brad W. Michael, Marc A. Gollub | 2021-01-26 |
| 10824504 | Common high and low random bit error correction logic | James A. O'Connor, Barry M. Trager, Warren E. Maule, Marc A. Gollub, Brad W. Michael | 2020-11-03 |
| 10824508 | High efficiency redundant array of independent memory | Christian Jacobi, Barry M. Trager | 2020-11-03 |
| 10747442 | Host controlled data chip address sequencing for a distributed memory buffer system | Steven R. Carlough, Susan M. Eickhoff, Warren E. Maule, Stephen J. Powell, Gary A. Van Huben +1 more | 2020-08-18 |
| 10684968 | Conditional memory spreading for heterogeneous memory sizes | David D. Cadigan, Thomas J. Dewkett, Glenn D. Gilda, Craig R. Walters | 2020-06-16 |
| 10673732 | Dynamic time-domain reflectometry analysis for field replaceable unit isolation in a running system | Luiz C. Alves, Christopher N. Oelsner, Gary A. Peterson, Christopher W. Steffen | 2020-06-02 |
| 10666540 | Dynamic time-domain reflectometry analysis for field replaceable unit isolation in a running system | Luiz C. Alves, Christopher N. Oelsner, Gary A. Peterson, Christopher W. Steffen | 2020-05-26 |
| 10642535 | Register access in a distributed memory buffer system | Steven R. Carlough, Markus Cebulla, Susan M. Eickhoff, Logan I. Friedman, Walter Pietschmann +2 more | 2020-05-05 |
| 10613951 | Memory mirror invocation upon detecting a correctable error | Marc A. Gollub, Warren E. Maule | 2020-04-07 |
| 10606692 | Error correction potency improvement via added burst beats in a dram access cycle | Paul W. Coteus, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule, James A. O'Connor +1 more | 2020-03-31 |
| 10601448 | Reduced latency error correction decoding | Glenn D. Gilda, Arthur J. O'Neill, Barry M. Trager | 2020-03-24 |
| 10558519 | Power-reduced redundant array of independent memory (RAIM) system | Glenn D. Gilda | 2020-02-11 |