| 12188979 |
Error protection analysis of an integrated circuit |
Benjamin Neil Trombley, Chung-Lung K. Shum, Karl Evan Smock Anderson, Erica Stuecheli, Shiri Moran +3 more |
2025-01-07 |
| 11657159 |
Identifying security vulnerabilities using modeled attribute propagation |
Matthew Michael Garcia Pardini, Zoltan T. Hidvegi, Michael P. Mullen |
2023-05-23 |
| 11501047 |
Error injection for timing margin protection and frequency closure |
Sean Michael Carey, Richard F. Rizzolo, Divya K. Joshi, Paul Jacob Logsdon, Sreekala Anandavally +1 more |
2022-11-15 |
| 10896118 |
Determine soft error resilience while verifying architectural compliance |
Ophir Erez, Divya K. Joshi, Gerrit Koch, Parminder Singh |
2021-01-19 |
| 10614192 |
Ranking combinations of mutants, test cases and random seeds in mutation testing |
Peng Fei Gou, Yang Li, Dan Liu, Yang Liu |
2020-04-07 |
| 10437699 |
Measuring execution time of benchmark programs in a simulated environment |
Sascha Eckmann, Thomas Gardelegen, Wolfgang Gellerich |
2019-10-08 |
| 10430311 |
Measuring execution time of benchmark programs in a simulated environment |
Sascha Eckmann, Thomas Gardelegen, Wolfgang Gellerich |
2019-10-01 |
| 10318406 |
Determine soft error resilience while verifying architectural compliance |
Ophir Erez, Divya K. Joshi, Gerrit Koch, Parminder Singh |
2019-06-11 |
| 9965580 |
Ranking combinations of mutants, test cases and random seeds in mutation testing |
Peng Fei Gou, Yang Li, Dan Liu, Yang Liu |
2018-05-08 |
| 9727754 |
Protecting chip settings using secured scan chains |
Benedikt Geukes, Matteo Michel, Juergen Wakunda |
2017-08-08 |
| 9600616 |
Assuring chip reliability with automatic generation of drivers and assertions |
Eli Arbel, Erez Barak, Udo Krautz, Shiri Moran |
2017-03-21 |
| 9483591 |
Assuring chip reliability with automatic generation of drivers and assertions |
Eli Arbel, Erez Barak, Udo Krautz, Shiri Moran |
2016-11-01 |
| 9443044 |
Determining a quality parameter for a verification environment |
Peng Fei Gou, Dan Liu, Yong Pan |
2016-09-13 |
| 9222973 |
Protecting chip settings using secured scan chains |
Benedikt Geukes, Matteo Michel, Juergen Wakunda |
2015-12-29 |
| 9098653 |
Verifying processor-sparing functionality in a simulation environment |
Stefan Letz, Joerg Deutschle, Erica Stuecheli, Brian W. Thompto |
2015-08-04 |
| 9015025 |
Verifying processor-sparing functionality in a simulation environment |
Stefan Letz, Joerg Deutschle, Erica Stuecheli, Brian W. Thompto |
2015-04-21 |
| 7565636 |
System for performing verification of logic circuits |
Christoph Jaeschke, Johannes Koesters |
2009-07-21 |
| 7398494 |
Method for performing verification of logic circuits |
Christoph Jaeschke, Johannes Koesters |
2008-07-08 |
| 7353159 |
Method for parallel simulation on a single microprocessor using meta-models |
Frank Armbruster, Johannes Koesters, Klaus-Dieter Schubert |
2008-04-01 |
| 7213220 |
Method for verification of gate level netlists using colored bits |
Christoph Jaeschke, Johannes Koesters |
2007-05-01 |
