Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9098637 | Ranking process for simulation-based functional verification | Bijaya Kumar Sahu, Hannes Froehlich, Sandeep Pagey | 2015-08-04 |
| 8560985 | Configuration-based merging of coverage data results for functional verification of integrated circuits | Bijaya Kumar Sahu, Sandeep Pagey, Hannes Froehlich | 2013-10-15 |
| 8413088 | Verification plans to merging design verification metrics | Sandeep Pagey, F. Erich Marschner, Dan Leibovich, Alok Jain, Axel Scherer +1 more | 2013-04-02 |
| 7353159 | Method for parallel simulation on a single microprocessor using meta-models | Bodo Hoppe, Johannes Koesters, Klaus-Dieter Schubert | 2008-04-01 |