SP

Sandeep Pagey

CS Cadence Design Systems: 7 patents #204 of 2,263Top 10%
Overall (All Time): #739,044 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9098637 Ranking process for simulation-based functional verification Bijaya Kumar Sahu, Frank Armbruster, Hannes Froehlich 2015-08-04
8560985 Configuration-based merging of coverage data results for functional verification of integrated circuits Bijaya Kumar Sahu, Frank Armbruster, Hannes Froehlich 2013-10-15
8527936 Method and system for implementing graphical analysis of hierarchical coverage information using treemaps Anuja Jain, Yaron Peri-Glass 2013-09-03
8413088 Verification plans to merging design verification metrics Frank Armbruster, F. Erich Marschner, Dan Leibovich, Alok Jain, Axel Scherer +1 more 2013-04-02
8214782 Systems for total coverage analysis and ranking of circuit designs Swapnajit Chakraborti, Boris Gommershtadt, Yael Duek-Golan 2012-07-03
7890902 Methods and apparatus for merging coverage for multiple verification and design scenarios Bijaya Kumar Sahu, Abhishek Kanungo, Christer Cederberg 2011-02-15
7886242 Systems, methods, and apparatus for total coverage analysis and ranking of circuit designs Swapnajit Chakraborti, Boris Gommershtadt, Yael Duek-Golan 2011-02-08